Design & Reuse
Catalog of SIP Cores
System on Chip design resources
4921 IP
4901
0.0
Nuclei N300: Low-power 3-stage-pipeline processor with DSP/FPU capable for embedded applications
High-performance 32-bit RISC-V core, Nuclei's most widely adopted, feature-rich embedded core. Suitable for complex real-time embedded applications, w...
4902
0.0
Nuclei N600(SMP): 32-bit high-efficiency 6-stage-pipeline processor with DSP/FPU capable for embedded and real-time applications
32-bit high-efficiency multi-core processor without MMU, comparable to ARM Cortex-R4/R5, based on the Nuclei 600 Series architecture, supporting 2–4 c...
4903
0.0
Nuclei NI1000: AI-optimized high-performance processor with advanced vector extension (up to 4096-bit) for high-end AI and HPC applications
64-bit high-end high-throughput RISC-V core, belonging to Nuclei 1000 series with out-of-order execution architecture. It adopts 2-wide decode design,...
4904
0.0
Nuclei NI900: AI-optimized high-performance processor with advanced vector extension (up to 1024-bit) for AI applications
64/32-bit high-performance RISC-V core, supporting single-core and cluster SMP configurations. Equipped with powerful VPU, FPU and crypto accelerators...
4905
0.0
Nuclei NS100: 32-bit ultra-low-power 2-stage-pipeline secure processor for EAL 5+ secure embedded applications
32-bit ultra-low-power RISC-V core, designed for ultra-low-power MCU, IoT and other low-power applications. A competitive rival to ARM SC000, with mi...
4906
0.0
Nuclei NS300: 32-bit low-power 3-stage-pipeline secure processor for EAL 5+ secure embedded applications
32-bit security-enhanced low-power RISC-V core, evolved from Nuclei N300 with enhanced security features. A competitive rival to ARM SC300/M35P, combi...
4907
0.0
Nuclei U600(SMP): 32-bit high-efficiency 6-stage-pipeline processor (with MMU) for Linux-capable applications
32-bit high-efficiency RISC-V core with MMU, belonging to Nuclei 600 Series. Comparable to ARM Cortex-A5/A7, supporting 32-bit Linux system, balancing...
4908
0.0
Nuclei U900(SMP): 32-bit high-efficiency 9-stage-pipeline processor (with MMU) for Linux-capable applications
32-bit high-performance RISC-V core with MMU, belonging to Nuclei 900 Series. Comparable to ARM Cortex-A7/A9, supporting 32-bit Linux system, dual-iss...
4909
0.0
Nuclei UX600(SMP): 64-bit high-efficiency 6-stage-pipeline processor (with MMU) for Linux-capable applications
Entry-level 64-bit high-efficiency RISC-V core with MMU, belonging to Nuclei 600 Series. Comparable to ARM Cortex-A35/A53, supporting 64-bit Linux sys...
4910
0.0
Nuclei UX900(SMP): 64-bit high-efficiency 9-stage-pipeline processor (with MMU) for Linux-capable applications
64-bit high-performance RISC-V core with MMU, belonging to Nuclei 900 Series. Comparable to ARM Cortex-A35/A53/A55, dual-issue execution, supporting 6...
4911
0.0
Audio Codec
INNOSILICON™ Audio Codec IP is a low power, high resolution, stereo audio solution which leverages Sigma-Delta noise-shaping technology. The ADC, DAC,...
4912
0.0
PUF Security
A physical unclonable function, or PUF, is a "digital fingerprint" that serves as a unique identity for a semiconductor device such as a microprocesso...
4913
0.0
eUSB2 PHY
The industry’s most advanced process nodes do not support 3.3V signaling and 5V tolerance as required by the USB 2.0 specification. 3.3V signaling was...
4914
0.0
JVC_4K Adoptive Scaler + Super Resolution - Convert Full-HD to High quality 4k2k with super resolution technology
JVC s 4k2k Super Resolution IP is now available for licensing. It offers dramatically less jaggy and Full-HD to 4k2k up-conversion with high performan...
4915
0.0
LVDS RX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
4916
0.0
LVDS TX Combo TTL PHY
Innosilicon LVDS implements LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains four 7-bit parallel-load serial-out shift registers, a 7X clock...
4917
0.0
LVDS TX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
4918
0.0
LVDS/TTL PHY & Controller
INNOSILICON™ LVDS/TTL IP implements the LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface. It supports either...
4919
0.0
NVM EEPROM NeoEE in DBHitek(180nm, 90nm)
eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...
4920
0.0
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/ Low-K process, Two Port Register File memory compiler....
4921
0.0
Type-C PHY
Innosilicon Type-C IP is composed of the physical layer and the PHY logic. The physical layer contains 4 data channels, an AUX channel and bias circui...