Design & Reuse
15 IP
1
15.0
HBM3E Controller
Bandwidth and area optimized low power memory interface solution tuned for AI, HPC, data centers and networking conforming to HBM3 JEDEC standards...
2
15.0
High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
SkyeChip’s HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD238A) operating...
3
15.0
Coherent Network-on-Chip (NoC)
SkyeChip's NoC is the first in the world that is able to reconfigure routing paths after tapeout. It is a scalable and area efficient interconnect sol...
4
11.0
10.67Gbps LPDDR5/5X PHY & Controller
High performance, low power and area efficient memory interface solutions conforming to LPDDR5/5X (JESD209-5C) JEDEC standard. Extra RAS add-on featu...
5
11.0
Bandgap
...
6
11.0
HBM3 PHY & Controller
SkyeChip’s High Bandwidth Memory (HBM) IP consists of a PHY and memory controller optimized for TSMC N7, N12 and Samsung 4nm process to support the HB...
7
11.0
DDR5/4 PHY & Controller
DDR5/4 PHY & Controller...
8
11.0
Die-to-Die (D2D) Interconnect
Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead...
9
11.0
Die-to-Die (D2D) Interconnect
Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead...
10
11.0
High-Speed PLL
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11
11.0
MIPI D-PHY
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12
11.0
Configurable I/O
High-speed configurable I/O capable of signaling speeds of up to 3.2 GT/s supporting the following I/O standards...
13
7.0
Non-Coherent Network-on-Chip (NoC)
SkyeChip's NoC is the first in the world that is able to reconfigure routing paths after tapeout. Performance (throughput and latency) optimized no...
14
0.0
SkyeChip ASIC Solutions
SkyeChip ASIC team consists of highly accomplished IC designers with successful careers in designing multiple generations of Microprocessors, Chipsets...
15
0.0
Low Power RISCV CPU
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