Design & Reuse
909 IP
901
0.0
CXL 3.0 Dual Mode Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
902
0.0
CXL 3.0 Host Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
903
0.0
CXL 3.0 Retimer
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...
904
0.0
CXL Controller IP
The CXL Controller IIP core supports the CXL 1.0 and 1.1 Specification. Through its CXL compatibility, it provides a simple interface to a wide range ...
905
0.0
CXP Host IP
SmartDV’s CXP (CoaXPress) Host IP is a high-performance solution designed for machine vision, industrial inspection, and high-speed imaging applicatio...
906
0.0
DXTP GPU
Designed for efficiency. Programmed for performance.Artificial Intelligence is transforming smartphones, bringing one-click photo enhancements, intell...
907
0.0
Hybrid Memory Cube (HMC) Verification IP
HMC : Asiczen’s Verification IP for HMC provides a comprehensive set of protocol, methodology, verification and productivity features, enabling user t...
908
0.0
HyperFlash Memory Model
HyperFlash Memory Model provides an smart way to verify the HyperFlash component of a SOC or a ASIC. The SmartDV s HyperFlash memory model is fully co...
909
0.0
HyperRAM Memory Model
HyperRAM Memory Model provides an smart way to verify the HyperRAM component of a SOC or a ASIC. The SmartDV s HyperRAM memory model is fully complian...