Design & Reuse
970 IP
251
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PCIe 6.2 Switch IP Controller
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252
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PCIE Gen6 digital controller (Dual Mode)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...
253
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PCIE Gen6 digital controller (End Point)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...
254
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PCIE Gen6 digital controller (Root Complex)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...
255
0.0
PCIe GEN6 PHY
Designed for next-generation PCIe systems, the PCIe GEN6 PHY IP supports data rates up to 64GT/s per lane with advanced PAM4 signaling. It ensures eff...
256
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PCIe Gen6.0 Retimer
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...
257
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PCIE Gen7 Controller
Gen7 supports 128Gbps and backward compatible with previous versions of PCIE....
258
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HCL Technologies - SoC Turnkey Design
SoC Turnkey Design service provides a comprehensive solution for companies looking to develop custom System-on-Chip (SoC) solutions without the need f...
259
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MD5 Hashing Core
The es1005 hash fully implements the MD5 (Message Digest Algorithm RFC 1321). The core can be used for data authentication in digital broadband, wire...
260
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MD5 Message-Digest Algorithm
The MD5 core from Alma Technologies is a high-performance implementation of the MD5 Message-Digest algorithm, a one-way hash function, compliant to th...
261
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HDCP Encryption-Decryption Engine
The Trilinear Technologies High-bandwidth Digital Content Protection (HDCP) Encryption-Decryption Engine IP core allows system designers to accelerate...
262
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Edge Computing Microprocessor for Space Applications
Ready for Space, Built for the Edge. Transforming the high-performance edge with the VA7230. Previously, GPU solutions were only possible with FPGA ...
263
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DDR5 CKD 01 - Clock Driver
The DDR5CKD01 is a registering clock driver used on DDR5 CUDIMMs, CSODIMMs, and CAMM. Its primary function is to buffer the DDR clock between the Host...
264
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DDR5 Power Management IC
Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application. PMIC is used for switching and LDO regulators. PMIC-I3C I...
265
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DDR5 REGISTERING CLOCK DRIVER (RCD) IP - DDR5RCD03
The DDR5RCD03 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs. Its primary function is to buffer the Command/Address (CA) bus, chip sele...
266
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DDR5 Serial Presence Detect (SPD5) Hub Interface
The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), fro...
267
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DDR5 Temperature Sensor - TS5111 and TS5110
he TS5111 and TS5110 device incorporate thermal sensing capability which is controlled and read over two wire bus. These device operate on I2C and I3C...
268
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LDS High Speed JPEG Codec - High Speed Low Power JPEG Codec IP Core
High Speed Low Power JPEG Codec IP Core...
269
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Advanced Encryption Standard (AES) Engine
ParaQum Technologies® advanced Encryption Standard (AES) engine is a highly configurable and multipurpose encryption/decryption engine. The AES en...
270
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Vector processor
World\'s first audio DSP IP with vector processor architecture From early Motorola and TI DSPs to modern smartphone DSPs in application processors, D...
271
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Serial Peripheral Interconnect Master & Slave Interface Controller
The SPI-MS core from Alma Technologies implements a Serial Peripheral Interconnect interface controller, which can operate either as a Master or a Sla...
272
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AES 256 encryption IP core
Logic Fruit’s AES 256 encryption IP core implements Rijndael encoding and decoding. It works with 256-bit blocks and is programmed to work with 256-bi...
273
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AES Core
The es4001 AES core implements the Advanced Encryption Standard (Rijndael Algorithm FIPS 197) encoder and decoder. The core encrypts and decrypts in b...
274
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DES Core - Low-gate count Data Encryption Standard
ES1040 core implements Data Encryption Standard (DES) cipher algorithms in hardware. DES is a block cipher, works on blocks of 64 bits of data using 6...
275
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AES Encryption & Decryption with Fixed Block Cipher Mode AES-C
The Alma Technologies AES-C IP Core implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks of...
276
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AES Encryption & Decryption with Programmable Block Cipher Mode AES-P
The Alma Technologies AES-P IP Core implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks of...
277
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JESD204B Transmitter and Receiver
Logic fruit Technologies has designed JESD204B RTL IP. It can support increased lane rates upto 12.5Gbps for higher bandwidth applications. It can be ...
278
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JESD204C Transmitter and Receiver
Logic fruit Technologies has designed JESD204C RTL IP to support increased lane rates upto 32Gbps for higher bandwidth applications. This IP can be co...
279
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Neural Network Accelerator
The new PowerVR Series2NX Neural Network Accelerator (NNA) delivers high performance computation of neural networks at very low power consumption in m...
280
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1G UDP IP Stack
Logic Fruit’s 1G UDP IPⓇ is specialized in data transmission and reception over the internet. The UDP Protocol helps to establish a low-latency and lo...
281
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SHA-1 Hashing Core
The ES1002 hash core fully implements the SHA-1 (Secure Hash Algorithm RFC 3174). The core can be used for data authentication in digital broadband, w...
282
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SHA-1 Secure Hash Function
The SHA1 core from Alma Technologies is a high performance implementation of the SHA-1 (Secure Hash Algorithm 1) one-way cryptographic hash function, ...
283
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SHA-256 Secure Hash Function
The Alma Technologies SHA256 IP core is a high performance implementation of the SHA-256 Message Digest algorithm, a one-way hash function, compliant ...
284
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VIA VAB-820 Pico-ITX ARM Board for IoT
Powered by a 1.0GHz NXP i.MX 6QuadPlus Cortex-A9 ARM SoC with enhanced graphics and memory performance or a 1.0GHz NXP i.MX 6Quad Cortex-A9 SoC, the V...
285
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High Bandwidth Memory (HBM) Verification IP
HBM: HBM (High Bandwidth memory) is a high performance RAM interface for 3D-stacked DRAM. HBM has been adopted as industry standard by JEDEC. ...
286
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High performance GPU for cloud gaming with DirectX support
IMG DXD is the first product in a new line of high-performance GPU IP with support for DirectX*. Starting with DirectX Feature Level 11_0, IMG DXD is ...
287
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High performance GPU for cloud gaming with DirectX support
IMG DXD is the first product in a new line of high-performance GPU IP with support for DirectX*. Starting with DirectX Feature Level 11_0, IMG DXD is ...
288
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High Performance RISC-V Processor for Edge Computing
Vector Instruction Set Support，Extended Vector Length Enhanced vector unit design optimized for machine learning workloads...
289
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High Profiles H.264 Encoder H264-HP-E
The Alma Technologies H264-HP-E IP Core is an advanced ITU-T H.264 High profiles hardware only encoder. It supports real time encoding of 4:2:0 and 4:...
290
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High Throughput Additive White Gaussian Noise Generator
A configurable AWGN generator that can be used as emulator of a noisy transmission channel and can support very high throughput rates up to 10 Gbps....
291
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High-efficiency real-time scalar RISC-V CPU core
R core can work standalone or integrate with several RiVAI-V cores in heterogeneous multicore products. Heterogeneous multicore architecture unleashes...
292
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MIL1553B IP Core
MIL-STD-1553B defines specifications for terminal device operation and coupling, word structure and format, messaging protocol and electrical characte...
293
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MIL1553B IP Core
MIL-STD-1553B defines specifications for terminal device operation and coupling, word structure and format, messaging protocol and electrical characte...
294
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Silicon Engineering Services
MosChip Technologies is a trusted partner for Silicon Engineering Services offering Turnkey ASIC, Silicon design and IP services (integration/porting/...
295
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LIN Master Slave Controller
Local Interconnect Network (LIN) is a broadcasting, Single Master, and Multi Slave (up to 16) communication protocol designed to support those feature...
296
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Single, Dual and Quad SPI Flash Controller with Boot and Execute On-The-Fly Features
The SPI-MEM-CTRL core from Alma Technologies offers the interconnection between a host and an SPI Flash memory device. The SPI-MEM-CTRL supports Singl...
297
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PIPE 4.3 compliant PHY Verification IP
azPHY 1.0 is a perfect solution to verify high speed interface serdes IPs that support the high speed standards e.g. PCIe, USB and SATA. This VIP cons...
298
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RISC V - CORE DEVELOPMENT
RISC-V (pronounced risk-five ) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015...
299
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RISC-V Base + Standard Extensions CPU Core Verification
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300
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Display Stream Compression (DSC 1.2) Decoder
The Trilinear Technologies Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions fro...