Design & Reuse
5490 IP
1
70.0
ISP, Image Signal Processing, Real-time Pixel Processor for Automotive
Dream Chip’s Real-time Pixel Processor (RPP) is a scalable and configurable High Dynamic Range (HDR) capable image signal processor (ISP), develo?ped ...
2
13.0
UHD Image Signal Processing (ISP) Pipeline
The logiISP Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital processing and image quality ...
3
1.0
Digital Signal Processing IP
VeriSilicon's programmable ZSP Digital Signal Processor IP is a series of processor cores optimized for signal processing computation and data streami...
4
1.0
Digital Signal Processing IP
VeriSilicon's programmable ZSP Digital Signal Processor IP is a series of processor cores optimized for signal processing computation and data streami...
5
1.0
Digital Signal Processing IP
VeriSilicon's programmable ZSP Digital Signal Processor IP is a series of processor cores optimized for signal processing computation and data streami...
6
1.0
Digital Signal Processing IP
ZSPNano is the perfect choice for Always ON applications involving sound detection, voice quality enhancement and command recognition. It is a tiny, ...
7
1.0
Digital Signal Processing IP
ZSPNano+ is a small, energy efficient, Digital Signal Processor Core for high performance Voice/Audio/Wireless applications. The compiler friendly a...
8
1.0
Digital Signal Processing IP-ZSPNano
ZSPNano is the perfect choice for Always ON applications involving sound detection, voice quality enhancement and command recognition. It is a tiny, e...
9
1.0
Image Signal Processing IP
The ISP8200 Series ISP is high performance ISP designed for products requiring the processing of multiple camera streams, particularly in automotive, ...
10
0.118
FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implement a signal processing solution for scanners, video and imaging applications. _x005F_x005F_x005F_x000D_
FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implem...
11
0.0
ACAP HDR Image Signal Processing Framework
The logiREF-ACAP-MULTICAM-ISP ACAP HDR Image Signal Processing Framework enables Xylon logiVID-ACAP-ISP HDR ISP Evaluation Kit for Versal ACAP users t...
12
0.0
ADAS Signal Processing
The first stage in the autonomous vehicle system is the perception stage. The environment both near and further away is combined with localization dat...
13
0.0
Image Signal Processing (ISP) for Automotive ADAS (RPP X328)
Dream Chip’s Real-time Pixel Processor for Vision applications is a scalable and configurable High Dynamic Range (HDR) capable image signal processor ...
14
0.0
Image Signal Processing (ISP) for Automotive Vision (RPP X418)
Dream Chip’s Real-time Pixel Processor for Vision applications is a scalable and configurable High Dynamic Range (HDR) capable image signal processor ...
15
0.0
Image Signal Processing (ISP) for Industrial IoT (RPP M114)
Dream Chip’s Real-time Pixel Processor for Vision applications is a scalable and configurable Wide Dynamic Range (WDR) capable image signal processor ...
16
0.0
Image Signal Processing (ISP) for Industrial Robotics (RPP H114)
The H Series represents Dream Chip's scalable and configurable Standard Dynamic Range 12-bit ISP platform, delivering high-quality imaging with low la...
17
0.0
Image Signal Processing (ISP) for low-power Wearables / IoT (RPP H214)
The H Series represents Dream Chip's scalable and configurable Standard Dynamic Range 12-bit ISP platform, delivering high-quality imaging with low la...
18
0.0
Image Signal Processing (ISP) for Surveillance / Security (RPP W114)
The W Series represents Dream Chip's scalable and configurable Wide Dynamic Range 16-bit ISP platform, delivering high-quality imaging with low latenc...
19
0.0
Image Signal Processing (ISP) RTL IP for IR/Mono/RGB Bayer/RGB-IR/PDAF/HDR/Fish Eye/3A Sensors Image Process to Human/Machine Vision
Altek ISP RTL IPs have good image quality to deal with different types of image sensor(ie. IR/Mono/RGB Bayer/RGB-IR/PDAF/HDR/Fish eye/3A/….) into huma...
20
0.0
Image Signal Processing IP
Industry s smallest die size. Multiple processes have been validated and mass produced. Fully functionally, open source...
21
10.0
Differential Signal Receiver - TSMC 6FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
22
10.0
Differential Signal Receiver - TSMC N5
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
23
0.0
Multi-domain simulation at the system-level for mixed signal behavior modeling
The simulators implement various models of computation. Most of these models of computation can be viewed as a framework for component-based design, w...
24
70.0
ISP, Image Signal Procesing, Real-time Pixel Processor Automotive
Dream Chips Real-time Pixel Processor (RPP) is a scalable and configurable High Dynamic Range (HDR) capable image signal processor (ISP), developed fo...
25
16.0
USB2.0 Host Transceiver PHY
USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) and Low-Speed Transceiv...
26
12.0
PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling. It contains all necessary AFE ...
27
12.0
Serial ATA (SATA) I/II PHY IP CORE
SMS6000 is a Serial ATA gen I and gen II compliant PHY IP which supports SAPIS and Serial Attached SCCI (SAS) specifications both at 1.5 Gbp/s and 3.0...
28
12.0
Fibre-Channel Transceiver
SMS3000 is a fully integrated CMOS transceiver compliant with ANSI X3T11 Fiber Channel standards. It contains all necessary Clock synthesis, Clock Rec...
29
12.0
Gigabit Ethernet For Fiber & STP/COAX Transceiver PHY
Gigabit Ethernet Transceiver for Fiber, Short Length Copper, STP and COAX....
30
12.0
SONET/SDH OC-3 / OC-12 Transceiver/CDR PHY
Innovative architecture to meet the SDH/ Sonet Jitter Spec utilizing deep sub-micron single poly CMOS process Fully in compliance with ANSI, Bellcore...
31
12.0
USB 2.0 Device Transceiver PHY
...
32
12.0
USB 2.0 OTG On-The-Go Transceiver PHY
SMS USB 2.0 OTG Transceiver is LS/FS/HS compliant with USB 2.0 specification and includes VBUS comparators, Switched Pullup & Pulldown resistors, data...
33
10.0
64x8 Bits OTP (One-Time Programmable) IP, X-FA- 0.18μm XH018 Modular Mixed Signal Process
The ATO00064X8XH180TG33NA is organized as a 64-bit by 8 one-time programmable (OTP). This is a type of non-volatile memory fabricated in X-FA- 0.18μm ...
34
1.0
VCC Detector to detects 1.2V core supply, output 3.3V digital signal
The present IP is a VCC Detector (VDT) circuit with normal operating voltage ranging from 1.08V ~1.32V. It first detects the core supply and then give...
35
1.0
Signal Ground Bias Voltage, Tunable - XFAB 180nm
Signal Ground Bias Voltage, Tunable - XFAB 180nm...
36
1.0
Time aligned Signal Generator core
The Signal Generator from NetTimeLogic is a clock aligned pulse and pattern (PWM) generator with nanosecond resolution (second and nanosecond format)....
37
1.0
Time aligned Signal Timestamper core
The Signal Timestamper from NetTimeLogic is a timestamper with nanosecond resolution (second and nanosecond format). It uses NetTimeLogic's Adjustable...
38
0.118
24-bit digital signal processor soft core.
24-bit digital signal processor soft core....
39
0.118
16-bit digital signal processor soft core.
16-bit digital signal processor soft core....
40
0.118
16-bit digital signal processor soft core._x005F_x005F_x005F_x005F_x005F_x000D_
16-bit digital signal processor soft core....
41
0.118
Receive the high speed serial signal, transfer it to parallel data and unpack the symbol packet, direct video stream output finally.
Receive the high speed serial signal, transfer it to parallel data and unpack the symbol packet, direct video stream output finally....
42
0.118
UMC 28nm HPC Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format
UMC 28nm HPC Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format...
43
0.118
UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format
UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format...
44
0.0
512x1 Bits OTP (One-Time Programmable) IP, TSM- 152nm 1.8V/3.3V Mixed Signal
The ATO00512X1TS152GMS3NA is organized as a 512-bits by 1 one-time programmable in parallel mode. This is a kind of non-volatile memory fabricated in...
45
0.0
512x8 Bits OTP (One-Time Programmable) IP, SMI- 110nm 1.2V/3.3V Mixed Signal Generic Process
The AT512X8Z110LLSAA is organized as 512 bits by 8 one-time programmable in 8-bit read and 1-bit program modes. This is a kind of non-volatile memory ...
46
0.0
512x8 Bits OTP (One-Time Programmable) IP, SMI- 110nm 1.2V/3.3V Mixed Signal Generic Process
The AT512X8Z110LL0AA is organized as a 512-bit by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in SMI- 110nm 1.2V/3...
47
0.0
128x8 Bits OTP (One-Time Programmable) IP, SMI- 0.18µm 1.8V/3.3V Mixed Signal Process
The AT128X8Z180MH0AA is organized as a 128-bit by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in 0.18µm standard ...
48
0.0
128x8 Bits OTP (One-Time Programmable) IP, SMI- 110nm 1.2V/3.3V Mixed Signal HE Process
The AT128X8Z110LL0AA is organized as 128 bits by 8 one-time programmable in 8-bit read and 1-bit program modes. This is a kind of non-volatile memory ...
49
0.0
32x8 Bits OTP (One-Time Programmable) IP, VI- 0.25μm 2.5V/3.3V Mixed Signal Process
The ATO00032X8VI250MS03NA is organized as a 32-bit by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in VI- 0.25μm 2....
50
0.0
256x16 Bits OTP (One-Time Programmable) IP, 256x16 Bits One Time Programmable Device SMI- 110nm 1.2V/3.3V Mixed Signal Generic Process
The AT256X16Z110LL0AA is organized as 256 bits by 16 one-time programmable in 16-bit read and 1-bit program modes. This is a kind of non-volatile memo...