Design & Reuse
4908 IP
1301
70.0
DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1302
70.0
LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1303
70.0
LPDDR5X/5/4X/4 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1304
60.0
UCIe Chiplet PHY & Controller
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
1305
60.0
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology...
1306
50.0
High Bandwidth Out-of-Order RISC-V CPU IP Core
...
1307
50.0
High Bandwidth Out-of-Order RISC-V CPU IP Core
...
1308
50.0
LPDDR5/4x/4 combo PHY on 14nm, 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1309
46.0
32Gbps, 31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions reg...
1310
46.0
32Gbps, 7/15 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7 or 15 order, up to 32Gbps. Error count is accurate: no double counts or omission...
1311
46.0
32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7, 15 or 31 order, up to 32Gbps. Error count is accurate: no double counts or omis...
1312
40.0
LPDDR5X/5/4X/4 combo PHY at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1313
40.0
LPDDR5X/5/4X/4 PHY for 16nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
1314
40.0
LPDDR5X/5/4X/4 PHY IP for 12nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
1315
30.0
4-/8-bit mixed-precision NPU IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1316
30.0
UCIe Die-to-Die Chiplet Controller
Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...
1317
30.0
UFS Host Controller 4.1 IP
The UFS Host Controller Interface (UFSHCI) is a high-performance interface that connects to UniPro and M-PHY IP in mobile platforms. It provides comma...
1318
30.0
High speed NoC (Network On-Chip) Interconnect IP
OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OIC is the ORBIT high-speed On-chip In...
1319
30.0
Highly scalable inference NPU IP for next-gen AI applications
OPENEDGES, the total memory subsystem IP provider, introduces ENLIGHT Pro, a state-of-the-art inference neural processing unit (NPU) IP that outperfor...
1320
30.0
RISC-V Tensor Unit
The bulk of computations in Large Language Models (LLMs) is in fully-connected layers that can be efficiently implemented as matrix multiplication. Th...
1321
30.0
All in one solution for AI in RISC-V
...
1322
29.0
USB V3.1 Power Delivery Type-C Port Evaluation board for OTI9108 IP
The OTS9106 board is a complete FPGA and ARM processor based USB PD Type-C port, featuring the RTL and C source code of the Obsidian Technology OTI910...
1323
25.0
HBM4, HBM3E PHY & Controller
INNOSILICON™ HBM4/3E IP is fully compliant with the JEDEC standard for HBM3E and the preliminary specification for HBM4. The IP includes a customizabl...
1324
25.0
DDR5, DDR4 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR5/4 Combo PHY s provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDR...
1325
25.0
Superscalar Out-of-Order Execution Multicore Cluster
AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on AndeStar™ V5 architectu...
1326
20.0
100Base-T1 Automotive Ethernet PHY
100Base-T1 Automotive Ethernet PHY...
1327
20.0
PCIe 4.0 PHY in TSMC(6nm,7nm,12nm,16nm)
M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 4.0 IP suppo...
1328
20.0
PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
M31 PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 5.0 IP suppo...
1329
20.0
GDDR6 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1330
20.0
High Performance HBM, HBM3 Memory Controller
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1331
20.0
MIPI C-PHY/D-PHY Combo(5nm, 7nm, 12/16nm, 28nm, 40nm, 55nm)
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
1332
20.0
MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pi...
1333
20.0
LPDDR4/3, DDR4/3 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1334
20.0
LPDDR4x/4 PHY IP for 22nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1335
20.0
LPDDR5X/5/4X/4 combo PHY at 12nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
1336
20.0
USB4 Gen3X2 and DP1.4 X4 PHY IP with Type-C connector support
M31 USB4 Gen3x2 transceiver IP provides a complete range of USB4 Gen3x2 host and peripheral applications up to 40Gbps. It is compliant with the PIPE5....
1337
15.5556
SMD RISC-V SDK
Quickly and seamlessly develop, debug and fine-tune applications for Semidynamics RISC-V hardware with the SMD RISC-V SDK. It is a complete software d...
1338
15.0
GDDR6X, GDDR6 Combo PHY & Controller
The INNOSILICON™ GDDR6X/6 PHY is fully compliant with the JEDEC GDDR6X/6 standard, supporting data rates of up to 20 Gbps per pin for PAM2 GDDR6 mode ...
1339
11.0
NVM Anti-Fuse OTP NeoFuse in DBHitek(90nm)
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...
1340
11.0
NVM Anti-Fuse OTP NeoFuse in GLOBALFOUNDRIES (55nm, 40nm, 28nm, 22nm, 12nm)
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...
1341
11.0
NVM Anti-Fuse OTP NeoFuse in HHNEC (55nm)
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...
1342
11.0
NVM Anti-Fuse OTP NeoFuse in HLIC (28nm)
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...
1343
11.0
NVM Anti-Fuse OTP NeoFuse in Huali (55nm, 28nm)
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...
1344
11.0
NVM Anti-Fuse OTP NeoFuse in Maxchip (90nm, 80nm, 55nm, 40nm)
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...
1345
11.0
NVM Anti-Fuse OTP NeoFuse in NEXCHIP (90nm, 55nm, 40nm)
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...
1346
11.0
NVM Anti-Fuse OTP NeoFuse in Samsung (130nm, 28nm)
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...
1347
11.0
NVM Anti-Fuse OTP NeoFuse in SKHYNIX (90nm)
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...
1348
11.0
NVM Anti-Fuse OTP NeoFuse in SMIC (90nm, 55nm, 40nm, 28nm)
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...
1349
11.0
NVM Anti-Fuse OTP NeoFuse in TSMC (130nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm, 16nm, 12nm, N7, N6, N5, N5A, N4P)
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...
1350
11.0
NVM Anti-Fuse OTP NeoFuse in UMC (110nm, 80nm, 55nm, 40nm, 28nm, 22nm)
NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being highly reliable and secure. It provides non-...