Design & Reuse
4908 IP
151
5.0
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
152
5.0
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
153
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
154
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
155
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
156
5.0
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
157
5.0
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
158
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
159
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
160
5.0
SAS 4 Port 12G Recorder
The SAS Recorder IP Core provides an ready to use solution for high speed data recording applications. Simple interface guarantees fast time to marke...
161
5.0
SAS Initiator, 12G, 4 Ports, 48 Gbps, SATA Host
The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment of mass storage devi...
162
5.0
SATA Device IP Core (1.5, 3.0, 6.0 Gbps)
The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage ...
163
5.0
DDI Color Enhancement (CLREN) IP
BTREE's Color Enhancement IP modifies or emphasizes color by controlling Saturation/Luminance/Hue. BTREE's Color Enhancement can only adjust the color...
164
5.0
DDI High Dynamic Range IP
HDR improves the visibility of the output image compared to the input images by increasing the contrast of the image/video reproduced on the display. ...
165
5.0
Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s)
The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The ...
166
5.0
Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s) for Xilinx UltraScale
The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The ...
167
5.0
Visually LossLess compression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS)
TMC’s JPEG XS encoder / decoder IP is Visually LossLess compression / decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). T...
168
5.0
Visually LossLess decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS)
TMC’s JPEG XS encoder / decoder IP is Visually LossLess decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). The logic gate ...
169
5.0
Compact LossLess Decoder RTL Core
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170
5.0
Compact LossLess Encoder RTL Core
...
171
5.0
Lossless / Near lossless Encoder / Decoder Hardware IP
- Lossless / near lossless hardware encoder and decoder IP that features compact and high speed with TMC original algorithm. - Optimized logic gate...
172
5.0
JPEG Decoder 1-pixel/clock
- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency - Suitable for ...
173
5.0
JPEG Encoder 1-pixel/clock
- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency - Suitable for ...
174
5.0
Frame Rate Converter for 4K
TMC’s FRUC (Frame Rate Up-Converter) for 4K RTL Core utilizes proprietary ”DMNA- MEMC” (Motion Estimation and Motion Compensation) algorithm which gen...
175
4.0
DDI Scaler IP - BSCALE
BTREE’s BSCALE enlarges or reduces the input video to fit the panel size. Polynomial Interpolation (PI) is the basic algorithm, and also various metho...
176
4.0
DDI Scaler IP - MSCALE
BTREE’s MSCALE enlarges the input video to fit the panel size. Bi-Linear interpolation is the basic algorithm, and also various methods such as sharpn...
177
4.0
Reed Solomon Decoder IP Core
A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error c...
178
4.0
Reed Solomon Encoder IP Core
A high performance, fully configurable Reed Solomon Encoder IP Core that is intended for use in a wide range of applications requiring forward error c...
179
3.0
USB 2.0 (LS, FS & HS) On-The-Go IP Core
A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB ...
180
1.0
2.5V 12Bit pipeline analog to digital converter
TheS65LLV25_ADC_13 IP is a 2.5V 12Bit pipeline analog to digital converter capable of running at up to 100MHz conversion rate with 2Vp-p input range....
181
1.0
S13_DAC_03 CMOS 10-BIT 200MSPS+CURRENT-STEERING D/A Converter
The S13_DAC_03 is a 10-bit resolution, high performance, low power, current-steering CMOS digital-to-analog converter (DAC). The input update rate can...
182
1.0
12-bit 1M Differential Rail to Rail SAR ADC
The analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The ADC includes a core intern...
183
1.0
12-bit 8 Input 1M/200k SAR ADC)
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The IP includes a core intern...
184
1.0
12-Bit SAR ADC in GlobalFoundries 22nm FDSOI
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution. The ADC includes intern...
185
1.0
12-Bit SAR ADC in GlobalFoundries 22nm FDSOI
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution. The ADC includes intern...
186
1.0
32:1 serializer followed by sub-LVDS drivers
The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data. The LVDS drivers operate in s...
187
1.0
I2C Master and Slave
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for app...
188
1.0
650M LVDS transmitter, 5 channel
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...
189
1.0
Samsung 28nm FDSOI 1.8v/1.0v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By setting DM [3:0] ...
190
1.0
Samsung 28nm FDSOI 1.8v/1.0v APLL
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191
1.0
Samsung 28nm FDSOI 1.8v/1.0v LVDS Transmitter
...
192
1.0
Samsung 28nm FDSOI 1.8v/1.0v sub-LVDS Receiver
...
193
1.0
Samsung 28nm FDSOI Codec
The SEC28FDSOI18_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver amplifier, and audio PL...
194
1.0
Samsung 28nm FDSOI MIPI DPHY V1.1
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195
1.0
SAMSUNG 28nm FDSOI USB2.0 Dual Role PHY/OTG PHY
The USB 2.0 OTG PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB analog fro...
196
1.0
Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and USB3.0 Super-Speed A...
197
1.0
Samsung 28nm FDSOI USB3.0 Type-C PHY
...
198
1.0
Samsung 28nm Low Power Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Power Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexibly generate memory bloc...
199
1.0
Samsung 28nm Low Voltage Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Voltage Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexibly generate memory bl...
200
1.0
IBM 10SF 65nm 2.5v PLL
Designed for audio clock generation, this PLL integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a c...