Design & Reuse
Catalog of SIP Cores
System on Chip design resources
5397 IP
601
0.0
USB-C 3.2 DP/TX PHY AR in TSMC (N3P)
The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controllers (Device, Host, or...
602
0.0
USB2 Device Controller
The Synopsys USB 2.0 Device Controller enables ASIC/FPGA designers to implement a complete USB 2.0 Device interface. The USB 2.0 Device supports USB H...
603
0.0
USB4 PHY - SS SF2, North/South Poly Orientation
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
604
0.0
USB4 PHY IP for TSMC N3E
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
605
0.0
ASIL B Compliant MIPI CSI-2 CSE2 Security Module
MIPI CSI‑2 is a widely adopted high‑speed interface for transmitting still and video data from image sensors to processors across mobile, automotive, ...
606
0.0
ASIL B Ready PCIe 5.0 Integrity and Data Encryption (IDE) Security IP
PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to data center servers t...
607
0.0
ASIL-B Compliant 1G-25G MACsec Security Module (select configurations)
Data security between Ethernet-connected devices is expanding due to multiple factors: exponential growth of data containing sensitive and private inf...
608
0.0
ASIL-B Ready PUF Hardware Premium with key wrap and certification support
Anything that is connected to the internet is at risk, and connected vehicles are no exception. Every connected electronic component represents a pote...
609
0.0
ASIL-B Ready Synopsys SRAM PUF
Anything that is connected to the internet is at risk, and connected vehicles are no exception. Every connected electronic component represents a pote...
610
0.0
TSMC N3P 1.2V High-Speed Test IO MS add-on
AI and HPC are transitioning to chiplet-based designs to overcome scaling limits of monolithic SoCs and achieve superior performance. While heterogene...
611
0.0
TSMC N3P 1.2V IO Platform supporting cells with Additional Features
The AI and HPC industries are advancing toward chiplet-based designs to achieve superior performance, as traditional monolithic SoCs face scaling chal...
612
0.0
TSMC N3P 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
613
0.0
TSMC N3P Source Sync 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
614
0.0
TSMC N3P Source Sync 3DIO PHY
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
615
0.0
TSMC N5 Source Sync 3DIO Library
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
616
0.0
XSR PHY for TSMC N5
The Synopsys USR/XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip m...
617
0.0
STAR Hierarchical System (SHS) IP
Synopsys SLM STAR Hierarchical System (SHS) is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores...
618
0.0
STAR Memory System (SMS) Test & Repair IP
Synopsys SLM SMS IP is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or non-repairable embedded memories ...
619
0.0
STAR Memory System (SMS) Test & Repair IP for CAMs (Content Addressable Memories)
Synopsys SLM SMS CAM 6 IP can be used to perform Test, Repair and Diagnostics for Content Addressable Memories such as BCAM, TCAM, XYCAM...
620
0.0
STAR Memory System ECC IP
Synopsys SLM STAR ECC 6 IP is a stand-alone product used to mitigate against soft errors in memories with the goal of improving in-field reliability...
621
0.0
PUF FPGA-X Premium with key wrapping
FPGAs are widely used in mission-critical environments with specific processing needs. Motivations for copying or altering sensitive data or valuable ...
622
0.0
PUF FPGA-Xilinx Base
FPGAs are widely used in mission-critical environments with specific processing needs. Motivations for copying or altering sensitive data or valuable ...
623
0.0
PUF Software Base
The number of connected devices, machines, sensors, or things that are linked with each other over open communication networks on the Internet of Thin...
624
0.0
PUF Software Premium with key wrap and certification support
The number of connected devices, machines, sensors, or things that are linked with each other over open communication networks on the Internet of Thin...
625
0.0
Multiprotocol 10G PHY in TSMC (16nm, N7)
The multi-lane Synopsys IP Multi-Protocol 10G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio, meeting the growing need...
626
0.0
Multipurpose Security Protocol Accelerator, ASIL B compliant
Complex system-on-chip (SoC) requirements can include security at the MAC layer, VPN layer, and application layer. The SynopsysSecurity Protocol Accel...
627
0.0
eUSB 2.0 PHY for TSMC N3A
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
628
0.0
eUSB 2.0 PHY in TSMC (N5, N4P, N4C, N3E, N3P, N2P)
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
629
0.0
eUSB 2.0 PHY in TSMC (N5A, N3A) for Automotive
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
630
0.0
eUSB2V2 PHY in TSMC (22nm)
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
631
0.0
Automotive-Compliant Synopsys UCIe Controller IP
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
632
0.0
NVM MTP in DB HiTek (130nm)
Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...
633
0.0
NVM OTP in TSMC N5A for Automotive
One Time Programmable (OTP) Non-Volatile Memory (NVM) IP solution, based on XHF architecture, is designed to meet the challenges of advanced FinFET de...
634
0.0
Synopsys 112G Ethernet PHY IP for TSMC N6
The Synopsys 112G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
635
0.0
Synopsys 112G PHY for TSMC N7
Synopsys IP Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high perfor...
636
0.0
Synopsys 224G Ethernet PHY IP for TSMC N2P
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
637
0.0
Synopsys 224G Ethernet PHY IP for TSMC N3P
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
638
0.0
Synopsys 32G PHY NCS for TSMC N5
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
639
0.0
Synopsys Auto-Grade MIPI D-PHY Tx for TSMC N7
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
640
0.0
Synopsys Complete UFS 5.0 solution with UniPro 3.0 + M PHY v6.0 enables Gear6B 46.7 Gb/s, reduced power, and high bandwidth scalability
The Synopsys Universal Flash Storage (UFS) Host Controller IP is a standardbased serial interface engine for implementing the JEDEC UFS interface in c...
641
0.0
Synopsys Controller IP for cHBM4
The Synopsys HBM4 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM4 standard. It interoperates with Synops...
642
0.0
Synopsys DDR5 MRDIMM2 PHY IP for TSMC N3P
The Synopsys DDR5 MRDIMM2 PHY IP is part of a complete IP solution including PHY and Controller enabling ASIC, Application-specific standard products ...
643
0.0
Synopsys DDR5 PHY IP for TSMC N4C
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
644
0.0
Synopsys eUSB2V2 Device Controller IP
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
645
0.0
Synopsys HBM4 IP for TSMC N3P
Synopsys offers a complete HBM4 PHY IP solution for high-performance computing (HPC), AI, graphics, and networking ASIC, Application-Specific Standard...
646
0.0
Synopsys High Speed Ethernet Dual 800G MAC IP
The Synopsys 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 specification...
647
0.0
Synopsys High Speed Ethernet PCS IP up to 200G
The Synopsys Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a complete set of featu...
648
0.0
Synopsys High speed M PHY v6.0 delivers 46.7 Gb/s Gear6B, enhanced channel robustness, low power modes, and integration with UniPro/UFS
The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v6.0 specification, supports speeds up to 46.7 Gbps per lane. The IP ...
649
0.0
Synopsys High-Speed Test IO in TSMC N3P
AI and HPC are transitioning to chiplet-based designs to overcome scaling limits of monolithic SoCs and achieve superior performance. While heterogene...
650
0.0
Synopsys LPDDR6/5X/5 PHY IP for TSMC N2P
The Synopsys LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LP...