2001 1.0

UMC L80G 80nm Deskew PLL - 240MHz-1200MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2002 1.0

UMC L80G 80nm Deskew PLL - 480MHz-2400MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2003 1.0

UMC L80G 80nm Spread Spectrum PLL - 120MHz-600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2004 1.0

UMC L80G 80nm Spread Spectrum PLL - 240MHz-1200MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2005 1.0

UMC L80G 80nm Spread Spectrum PLL - 480MHz-2400MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2006 1.0

UMC L80GOD 80nm Clock Generator PLL - 150MHz-750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2007 1.0

UMC L80GOD 80nm Clock Generator PLL - 300MHz-1500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2008 1.0

UMC L80GOD 80nm Clock Generator PLL - 600MHz-3000MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2009 1.0

UMC L80GOD 80nm DDR DLL - 150MHz-750MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2010 1.0

UMC L80GOD 80nm DDR DLL - 200MHz-1000MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2011 1.0

UMC L80GOD 80nm Deskew PLL - 150MHz-750MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2012 1.0

UMC L80GOD 80nm Deskew PLL - 300MHz-1500MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2013 1.0

UMC L80GOD 80nm Deskew PLL - 600MHz-3000MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2014 1.0

UMC L80GOD 80nm Spread Spectrum PLL - 150MHz-750MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2015 1.0

UMC L80GOD 80nm Spread Spectrum PLL - 300MHz-1500MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2016 1.0

UMC L80GOD 80nm Spread Spectrum PLL - 600MHz-3000MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2017 1.0

UMC L90G 90nm Clock Generator PLL - 180MHz-900MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2018 1.0

UMC L90G 90nm Clock Generator PLL - 360MHz-1800MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2019 1.0

UMC L90G 90nm Clock Generator PLL - 90MHz-450MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2020 1.0

UMC L90G 90nm DDR DLL - 108MHz-540MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2021 1.0

UMC L90G 90nm DDR DLL - 144MHz-720MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2022 1.0

UMC L90G 90nm Deskew PLL - 180MHz-900MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2023 1.0

UMC L90G 90nm Deskew PLL - 360MHz-1800MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2024 1.0

UMC L90G 90nm Deskew PLL - 90MHz-450MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2025 1.0

UMC L90G 90nm Spread Spectrum PLL - 180MHz-900MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2026 1.0

UMC L90G 90nm Spread Spectrum PLL - 360MHz-1800MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2027 1.0

UMC L90G 90nm Spread Spectrum PLL - 90MHz-450MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2028 1.0

UMC L90GOD 90nm Clock Generator PLL - 125MHz-625MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2029 1.0

UMC L90GOD 90nm Clock Generator PLL - 250MHz-1250MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2030 1.0

UMC L90GOD 90nm Clock Generator PLL - 500MHz-2500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2031 1.0

UMC L90GOD 90nm DDR DLL - 144MHz-720MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2032 1.0

UMC L90GOD 90nm DDR DLL - 192MHz-960MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2033 1.0

UMC L90GOD 90nm Deskew PLL - 125MHz-625MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2034 1.0

UMC L90GOD 90nm Deskew PLL - 250MHz-1250MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2035 1.0

UMC L90GOD 90nm Deskew PLL - 500MHz-2500MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2036 1.0

UMC L90GOD 90nm Spread Spectrum PLL - 125MHz-625MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2037 1.0

UMC L90GOD 90nm Spread Spectrum PLL - 250MHz-1250MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2038 1.0

UMC L90GOD 90nm Spread Spectrum PLL - 500MHz-2500MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2039 1.0

UMC L90SP 90nm Clock Generator PLL - 120MHz-600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2040 1.0

UMC L90SP 90nm Clock Generator PLL - 240MHz-1200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2041 1.0

UMC L90SP 90nm Clock Generator PLL - 60MHz-300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2042 1.0

UMC L90SP 90nm DDR DLL - 60MHz-300MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2043 1.0

UMC L90SP 90nm DDR DLL - 80MHz-400MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2044 1.0

UMC L90SP 90nm Deskew PLL - 120MHz-600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2045 1.0

UMC L90SP 90nm Deskew PLL - 240MHz-1200MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2046 1.0

UMC L90SP 90nm Deskew PLL - 60MHz-300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2047 1.0

UMC L90SP 90nm Spread Spectrum PLL - 120MHz-600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2048 1.0

UMC L90SP 90nm Spread Spectrum PLL - 240MHz-1200MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2049 1.0

UMC L90SP 90nm Spread Spectrum PLL - 60MHz-300MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2050 1.0

Programmable Special IO in SMIC0.13um AR750S13 is a programmable special IO cell supporting various JEDEG standards, such as LVDS, LVTTL, LVCMOS-33/25/18/15, SSTL_3/2/18. The IP is extreme...