Design & Reuse
5634 IP
5551
0.0
Super-Fast, Configurable 16-bit 80251 Microcontroller Core
The S80251XC3 core implements a high-performance 16-bit microcontroller that executes the MCS®251 & MCS®51 instruction sets and includes a configurabl...
5552
0.0
eUSB 2.0 PHY for TSMC N3A
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
5553
0.0
eUSB 2.0 PHY in TSMC (N5, N4P, N4C, N3E, N3P, N2P)
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
5554
0.0
eUSB 2.0 PHY in TSMC (N5A, N3A) for Automotive
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
5555
0.0
eUSB2V2 PHY
Low voltage USB 2.0 supporting 4.8Gbps eUSB2V2 is primarily a performance enhancement to eUSB2 native mode to provide more bandwidth for peripherals,...
5556
0.0
eUSB2V2 PHY in TSMC (22nm)
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
5557
0.0
Automotive Four Channel (4CH) LVDS Receiver (Deserializer) in TSMC 40LP
The AUTO-MXL-LVDS-4CH-RX-T-40LP is a high-performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel ...
5558
0.0
Automotive Four Channel (4CH) LVDS Transmitter (Serializer) in TSMC 40LP
The AUTO-MXL-LVDS-4CH-TX-T-40LP is a high-performance 4-channel LVDS transmitter implemented using digital CMOS technology. With a maximum transmit cl...
5559
0.0
Automotive LVDS TX+ (Transmitter) in UMC 40LP
The AUTO-MXL-LVDS-SR-TX+ is a high performance 4-channel LVDS transmitter implemented using digital CMOS technology. With a maximum transmit clock fre...
5560
0.0
Automotive MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 28HPM
The AUTO-MXL-DPHY-CSI-2-RX+ is a high frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for ...
5561
0.0
Automotive MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 40LP
The AUTO-MXL-DPHY-CSI-2-RX+-T-040LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Stand...
5562
0.0
Automotive MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+
The AUTO-MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY...
5563
0.0
Automotive MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 22ULL
The AUTO-MXL-DPHY-CSI-2-TX+-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specific...
5564
0.0
Automotive MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 28HPC+
The AUTO-MXL-DPHY-CSI-2-TX+-T028HPC+-RF-ULL is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specificati...
5565
0.0
Automotive MIPI D-PHY Universal IP in TSMC 16FFC
The AUTO-MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PH...
5566
0.0
Automotive MIPI D-PHY Universal IP in TSMC 28HPC+
The AUTO-MXL-DPHY-UNIV-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specific...
5567
0.0
Automotive MIPI D-PHY Universal IP in UMC 28HPC+
The AUTO-MXL-DPHY-UNIV-U-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificatio...
5568
0.0
Automotive MIPI D-PHY/LVDS Combo TX (Transmitter) in Samsung 28FDSOI
The AUTO-MXL-LVDS-DPHY-DSI-TX-SS-028FDSOI is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer sup...
5569
0.0
Automotive-Compliant Synopsys UCIe Controller IP
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
5570
0.0
LVDS Tx and OpenLDI Tx (Automotive IP)
InPsytech Inc., an Automotive interface IP solution provider, introduces its latest Automotive High-Speed Interface IP Series, designed to meet the ri...
5571
0.0
LVDS TX+ (Transmitter) in UMC 40LP
The MXL-LVDS-SR-TX+ is a high performance 4-channel LVDS transmitter implemented using digital CMOS technology. With a maximum transmit clock frequenc...
5572
0.0
NVM EEPROM NeoEE in DBHitek(180nm, 90nm)
eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foun...
5573
0.0
NVM OTP in GF (30nm, 65nm, 55nm, 40nm, 28nm, 22nm, 12nm)
Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...
5574
0.0
NVM OTP in TSMC N5A for Automotive
One Time Programmable (OTP) Non-Volatile Memory (NVM) IP solution, based on XHF architecture, is designed to meet the challenges of advanced FinFET de...
5575
0.0
NVMe Verification IP
Non Volatile Memory Express, also known as NVMe is an interface specification built for accessing Solid State Drive (SSD) over PCIe. NVMe has revoluti...
5576
0.0
1Watts, 2.1-2.8GHz Power Amplifier
...
5577
0.0
SWI3S Manager core IP
Arasan’s SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the...
5578
0.0
SWI3S Peripheral core IP
Arasan’s SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer ...
5579
0.0
Switch with 0/20dB Attenuator
...
5580
0.0
PWM to Class D Amplifier Power Stage, SMIC 0.13um
The AR35S13A is a highly efficient H-BTL audio output driver IP for Class-D amplifier application. The IP is capable of providing 0.1% THD+N performan...
5581
0.0
AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash...
5582
0.0
AXI Bus Display Controller
The Digital Blocks DB9000AXI3 Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect to...
5583
0.0
AXI Interconnect Fabric
The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Masters. AXI defines 5...
5584
0.0
AXI Interface Core
Rambus’s AXI Interface Core is designed for use in applications requiring ARM’s Advanced eXtensible Interface (AXI). The core accepts write and rea...
5585
0.0
AXI Multilayer Interconnect
The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric ...
5586
0.0
AXI Subsystem
The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces...
5587
0.0
AXI to AHB Lite Bus Bridge
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...
5588
0.0
AXI to APB Bridge
The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI bus. The highly con...
5589
0.0
AXI to APB Bus Bridge
The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one ...
5590
0.0
AXI4 Memory Map to AXI4-Stream Bridge
Digital Blocks DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the address to ...
5591
0.0
AXI64 5 Port SRAM Controller
The AXI 5-Master component SRAM Controller provides 5 AXI 64-bit Master components with low-wait-state access to a single internal 64-bit SRAM resourc...
5592
0.0
CXL Controller IP
The Wolley Compute Express Link® (CXL®) 3.1 controller is a highly-configurable design for ASIC and FPGA implementations. It maintains backward compat...
5593
0.0
CYB-SM3 Cryptographic Hash Function
SM3 is a hash algorithm initially published by the Office of State Commercial Cryptography Administration (OSCCA) of SCA in 2010, then as a China indu...
5594
0.0
CYB-SM4 Block Cipher Algorithm
SM4 (former name “SMS4”) is a cryptographic standard published by the Office of State Commercial Cryptography Administration (OSCCA) of SCA as an indu...
5595
0.0
Hybrid Memory Cube Verification IP
Atria Logic Hybrid Memory Cube verification IP is a reusable, configurable verification component developed using SystemVerilog. The IP offers an easy...
5596
0.0
Synopsys 112G Ethernet PHY IP for TSMC N6
The Synopsys 112G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
5597
0.0
Synopsys 112G PHY for TSMC N7
Synopsys IP Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high perfor...
5598
0.0
Synopsys 224G Ethernet PHY IP for TSMC N3P
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
5599
0.0
Synopsys 32G PHY NCS for TSMC N5
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
5600
0.0
Synopsys Auto-Grade MIPI D-PHY Tx for TSMC N7
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...