Design & Reuse
5634 IP
151
7.5
USB 3.0 Retimer (Exclusively for Turnkey ASIC design; not for standalone licensing)"
USB3.0 Retimer softcore is designed for use USB Port/Cable Retimer applications. The requirements set forth in the specification comprehend the use of...
152
7.5
Ethernet 10/100 MAC (Exclusively for Turnkey ASIC design; not for standalone licensing)
The Ethernet controller is compliant with IEEE802.3 and it provides an interface between the host subsystem and the Media Independent Interface (MII)....
153
5.0
H.264 Baseline Profile Encoder
The H264-BP-E core from Alma Technologies is an advanced H.264 hardware encoder that conforms to the ITU-T H.264 Constrained Baseline Profile. The cor...
154
5.0
H.264 Main Profile Encoder
The H264-MP-E core from Alma Technologies is an advanced H.264 hardware encoder that conforms to the Main Profile of the ITU-T H.264 standard. The cor...
155
5.0
Scalable UHD H.264 Encoder - Ultra-High Throughput, Intra frames (IDR) encoding
The UHT-H264E-IDR core from Alma Technologies is a scalable ultra-high throughput H.264 Intra encoder. It is designed to enable 4K UHD resolutions in ...
156
5.0
Scalable UHD H.264 Encoder - Ultra-High Throughput, Light Motion Estimation engine
The UHT-H264E-LME core from Alma Technologies is a scalable ultra-high throughput H.264 encoder equipped with a very compact Light Motion Estimation e...
157
5.0
Scalable UHD JPEG Decoder − Ultra-High Throughput, 8/10/12-bit per component
The UHT-JPEG-D core from Alma Technologies is a very high performance 8-bit Baseline and 12-bit Extended JPEG decoder, designed to enable the massive ...
158
5.0
MIPI I3C Master RISC-V based subsystem
RISC-V based MAXVY MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a ...
159
5.0
MIPI SPMI Target Controller
The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...
160
5.0
MIPI-I3C Combo Host and Target interface controller IP for Sensor and Peripheral connection
The MIPI I3C (Improved Inter Integrated circuit) is a two wire bidirectional Serial Bus for sensor communication. The MIPI I3C interface has been ...
161
5.0
MIPI-I3C Combo IP Host/Target HDR-DDR compliance with Spec v1.1.1
MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication. The MIPI I3C interface has been develope...
162
5.0
eNOR embedded Flash embedded IP
Zhuhai Chuangfeixin’s Floating-gate eNOR Flash memory macro are silicon characterized and qualified on Huali Microelectronics Corporation 65nm Floati...
163
5.0
OTP IP
Zhuhai Chuangfeixin (CFX) offers two proprietary OTP technologies and respective silicon IPs：One is Anti-fuse, the other is floating gate. CFX OTP ...
164
5.0
OTP One Time Programmable IP HHGrace 55HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
165
5.0
OTP One Time Programmable IP HHGrace 55LP
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
166
5.0
OTP One Time Programmable IP HHGrace 90BCD
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
167
5.0
OTP One Time Programmable IP HLMC 55CIS
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
168
5.0
OTP One Time Programmable IP Nexchip 110HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
169
5.0
OTP One Time Programmable IP Nexchip 110LP2
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
170
5.0
OTP One Time Programmable IP Nexchip 55HV_6V
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
171
5.0
OTP One Time Programmable IP Samsung 90CIS
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
172
5.0
OTP One Time Programmable IP SIL130HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
173
5.0
OTP One Time Programmable IP SIL180
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
174
5.0
OTP One Time Programmable IP Silterra 160HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
175
5.0
OTP One Time Programmable IP SMIC 153nm
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
176
5.0
OTP One Time Programmable IP SMIC 28HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
177
5.0
OTP One Time Programmable IP SMIC 55HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
178
5.0
OTP One Time Programmable IP SMIC130
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
179
5.0
OTP One Time Programmable IP XMC 55LL
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...
180
4.0
I2C Master Controller
The ntI2C_M is an I2C-bus multi-master interface controller and provides a cost-effective solution for a wide range of applications that require a low...
181
4.0
Additive White Gaussian Noise Generator
A configurable AWGN generator that can be used as emulator of a noisy transmission channel....
182
4.0
ADPCM G.726 Codec
The NTadpcm core is fully compliant with G.726 standard and supports up to 64 full duplex voice channels. The core is used in applications that requir...
183
4.0
IEEE 802.11 n/ac/ax LDPC Decoder
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The hig...
184
4.0
IEEE 802.11 n/ac/ax LDPC Encoder
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The hig...
185
4.0
OFDM Baseband Processor
Noesis Technologies ntOFDM_BBP is a custom baseband processor, which implements the physical layer of an OFDM, time division duplexing (TDD) system. T...
186
4.0
OFDM Baseband Processor
Noesis Technologies ntOFDM_BBP is a custom baseband processor, which implements the physical layer of an OFDM, time division duplexing (TDD) system. T...
187
4.0
OFDM synchronization unit
Noesis Technologies ntSYNC is a fully programmable component used to achieve time and frequency synchronization in OFDM technology physical layer impl...
188
4.0
SHA 256-bit hash generator
An n-bit hash is a map from arbitrary length messages to n-bit hash values. An n-bit cryptographic hash is an n-bit hash which is one-way and collisio...
189
4.0
High Throughput Additive White Gaussian Noise Generator
A configurable AWGN generator that can be used as emulator of a noisy transmission channel and can support very high throughput rates up to 10 Gbps....
190
4.0
High Throughput Rate OFDM Baseband PHY Processor
The ntOFDM_HS_BBP IP implements the physical layer transmission and reception processing engines of a custom subset of the 802.16-2012 standard. The n...
191
4.0
High Throughput Rate OFDM Baseband PHY Processor
The ntOFDM_HS_BBP IP implements the physical layer transmission and reception processing engines of a custom subset of the 802.16-2012 standard. The n...
192
4.0
Highly Integrated Reed Solomon Codec
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several ...
193
4.0
Single Channel HDLC Controller
Noesis Technologies ntHDLC single channel High-Level Data Link Controller (HDLC) is a full-duplex transceiver with independent transmit and receive un...
194
4.0
NIST FIPS-197 Compliant High Throughput Rate AES IP Core
ntAES128 core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of data usin...
195
4.0
NIST FIPS-197 Compliant Ultra-Low Power AES IP Core
ntAES8 core implements NIST FIPS-197 Advanced Encryption Standard. ntAES8 core can be programmed to encrypt or decrypt 128-bit blocks of data using a ...
196
4.0
Clock and Data Recovery of HDB3/B3ZS coded signals
An all-digital solution suitable for clock/data recovery of HDB3/B3ZS coded signals....
197
4.0
Ultra High Speed FFT/IFFT processor
Noesis Technologies ntFFT_UHS IP implements a customized FFT/IFFT programmable fixed point (Decimation in Frequency - DIF) transform processor, suppor...
198
4.0
Smart Grid PLC Baseband Processor
The ntG3_BBP is a fully compliant ITU-T G.9903 baseband modem that can be used in a wide range of smart grid applications over power lines, including ...
199
4.0
Interleaver / De-interleaver
Configurable interleaving/deinterleaving function that can be used in a wide range of applications that employ channel coding....
200
4.0
Home Plug Green PHY MAC Layer TX/RX
ntHPGP_MAC IP core implements “Connectionless CSMA-Only Level-0 CCo“ MAC Layer functionality with Passive Coordination, as detailed in Chapter 5 of “H...