Design & Reuse
1977 IP
1151
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process
TERMINUS-CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single &Quad-Lane PCI Express PHY that supports PCI Express protocol and...
1152
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
1153
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
1154
3.0
Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
Single Port Register File compiler - TSMC 55 nm LP - Memory optimized for high density and high speed - compiler range up to 40 k...
1155
3.0
Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
Single Port Register File compiler - TSMC 65 nm LP - Memory optimized for high density and high speed - compiler range up to 40 k...
1156
3.0
Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
Foundry sponsored - Single Port Register File compiler - TSMC 90 nm LPeF - Memory optimized for high density and high speed - compiler range up to 40 ...
1157
3.0
Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - compiler range up to 40 k
Foundry sponsored - Single Port Register File compiler - TSMC 90 nm uLL - high density - Dual Voltage - compiler range up to 40 k...
1158
3.0
Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits
Single Port Register File compiler - TSMC 90 nm uLL - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits...
1159
3.0
Single Port Register File compiler - Memory optimized for ultra high density and high speed - compiler range up to 20 k
Single Port Register File compiler - TSMC 110 nm HV_1.5V_5V_32V - Memory optimized for ultra high density and high speed - compiler range up to 20 k...
1160
3.0
Single Port Register File compiler - Memory optimized for ultra high density and high speed - compiler range up to 20 k
Foundry Sponsored - Single Port Register File compiler - TSMC 110 nm HV_1.5V_5V - Memory optimized for ultra high density and high speed - compiler ra...
1161
3.0
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
Single Port SRAM compiler - TSMC 110 nm HV_1.5V_5V_32V - Memory optimized for high density and low power - compiler range up to 320 k...
1162
3.0
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
Single Port SRAM compiler - TSMC 55 nm LPeF - Memory optimized for high density and Low power - compiler range up to 320 k...
1163
3.0
Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits
Single Port SRAM compiler - TSMC 90 nm uLL - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits...
1164
3.0
Single Port SRAM compiler - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k
Foundry sponsored - Single Port SRAM compiler - TSMC 55 nm HV - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 ...
1165
3.0
Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
Single Port SRAM compiler - TSMC 180 nm uLL - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k...
1166
3.0
Elliptic Curve Point Multiply and Verify Core
Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curves” and it is a part o...
1167
3.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-EW
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
1168
3.0
GMR Release 2 and GMR Release 3 LDPC Decoder
GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GM...
1169
3.0
Combined ChaCha20 and Poly1305 core
The eSi-CHACHA20-POLY1305 core is an easy to use APB hardware accelerator peripheral that is fully compliant with the IETF RFC7539 standard Poly1...
1170
3.0
FortifyIQ High-Performance Hybrid Classical and Post-Quantum High-assurance (SCA/DPA/FIA resistant) Cryptography IP Core (ECC/RSA, ML-KEM, ML-DSA)
FortifyIQ’s High-Performance Hybrid Cryptography IP core delivers accelerated support for both classical (RSA, ECC) and post-quantum (ML-KEM, ML-DSA) ...
1171
3.0
FortifyIQ HMAC-SHA256 Secure Core: Hardware Accelerator for SHA-2 and HMAC with Low Latency SCA/FI Protection
FortifyIQ’s SHA-2/HMAC IP core delivers high-speed, hardware-accelerated SHA-2-224/256 hashing and HMAC computation, optimized for secure embedded sys...
1172
3.0
FortifyIQ Hybrid Classical and Post-Quantum High-assurance (SCA/DPA/FIA resistant) Cryptography IP Core (ECC/RSA, ML-KEM, ML-DSA)
FortifyIQ’s Hybrid Cryptography IP core combines traditional asymmetric algorithms, such as RSA and ECC, with post-quantum standards including ML-KEM ...
1173
3.0
FortifyIQ's Compact DPA and FIA Hardened Post-Quantum ML-KEM IP Core for Resource-Constrained Devices (SCA/DPA/FIA resistant)
As quantum computing threatens traditional public-key cryptography, resource-constrained devices must adopt quantum-resistant algorithms without compr...
1174
3.0
Low-leakage LDO for logic and analog domains supply up to 5.5 Vin - High temperature (Grade 1, Tj=150°) in TSMC 40uLP
iLR-Victoria-OV-LS-ref-2.7-5.5-0.55-3.3.03_TSMC_40_uLP is a Low-leakage LDO in TSMC 40uLP to supply logic and analog domains (up to 5.5V input supply)...
1175
3.0
Low-leakage LDO for logic and analog domains supply up to 5.5 Vin - High temperature (Grade 1, Tj=150°) in TSMC 40uLPeF
iLR-Victoria-OV-LS-ref-2.7-5.5-0.55-3.3.03_TSMC_40_uLPeF is a Low-leakage LDO in TSMC 40uLPeF to supply logic and analog domains (up to 5.5V input sup...
1176
3.0
Low-leakage LDO to supply logic and analog domains (up to 3.63V input supply) in TSMC 22ULL
iLR-Victoria-ref-1.62-3.63-1.8-2.5.03_TSMC_22_ULL is a Low-leakage LDO in TSMC 22ULL to supply logic and analog domains (3.3V input supply)....
1177
3.0
Low-leakage LDO to supply logic and analog domains (up to 5.5V input supply) in SMIC 40eF
iLR-Victoria-OV-LS-ref-1.8-5.5-0.6-3.3.05_SMIC_40_EF is a Low-leakage LDO in SMIC 40eF to supply logic and analog domains (up to 5.5V input supply)....
1178
3.0
Low-leakage LDO to supply logic and analog domains (up to 5.5V input supply) in TSMC 40 ULP
iLR-Victoria-OV-ref-2.7-5.5-0.55-3.3.04_TSMC_40_uLP is a Low-leakage LDO in TSMC 40uLP to supply logic and analog domains (up to 5.5V input supply) wi...
1179
3.0
Power management unit (0.9V, 1.8V, 3.3V output voltages, 1.2V reference voltage and 10uA/1uA reference currents)
028TSMC_LDO_01 is a Power management unit, designed to supply integrated circuits with stable and precise voltage. IP includes Bandgap block, and 3 LD...
1180
3.0
LPDDR2/3/4/4x IP combo solution with high performance and low power
With sophisticated architecture and advanced technology, this LPDDR2/3/4/4x IP combo solution with high performance and low power. In 12~28nm CMOS pro...
1181
3.0
sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
Foundry sponsored - sROMet compiler - TSMC 55 nm uLP - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up...
1182
3.0
sROMet compiler - TSMC 40 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
sROMet compiler - TSMC 40 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M...
1183
3.0
True Random and Pseudorandom Number Generator
The true random generator core implements true random number generation. The core passes the American NIST Special Publication 800-22 and Diehard Rand...
1184
3.0
Dual Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 80 k
Foundry sponsored - Dual Port SRAM compiler - TSMC 90 nm LPeF - Memory optimized for high density and low power - compiler range up to 80 k...
1185
3.0
Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
Dual Port SRAM compiler - TSMC 40 nm uLP - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k...
1186
3.0
Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
Foundry sponsored - Dual Port SRAM compiler - TSMC 55 nm uLP - Memory optimized for high density and low power - Dual Voltage - compiler range up to 2...
1187
3.0
Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
Foundry sponsored - Dual Port SRAM compiler - TSMC 55 nm uLPeFlash - Memory optimized for high density and low power - Dual Voltage - compiler range u...
1188
3.0
Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
Dual Port SRAM compiler - TSMC 55 nm uLPeFlash - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k...
1189
3.0
DVB-C2 Receiver (including LDPC and BCH decoder)
DVB-C2 (Digital Video Broadcast - Cable 2nd Generation) is an ETSI standard of the second generation for digital data transmission via cable networks....
1190
3.0
DVB-S2 BCH and LDPC Encoder and Decoder
DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites....
1191
3.0
Switching regulator, inductor-based, in dual mode (PFM and PWM) & high efficiency in TSMC 55uLP
eSR-Niagara-Bu-dm-ref-1.62-3.63-0.8-2.5.01_TSMC_55_uLP is a DC/DC converter in TSMC 55uLP, flexible and readily re-targetable toward any sub micron CM...
1192
3.0
Switching regulator, inductor-based, in dual mode (PFM and PWM) & high efficiency in TSMC 55uLPeF
eSR-Niagara-Bu-dm-ref-1.62-3.63-0.8-2.5.01_TSMC_55_uLPeF is a DC/DC converter in TSMC 55uLPeF, flexible and readily re-targetable toward any sub micro...
1193
3.0
Switching regulator, inductor-based, in dual mode (PFM and PWM), high efficiency in TSMC 55uLPeF
eSR-Niagara-Bu-dm-ref-1.9-4.4-0.8-3.3.02_TSMC_55_uLPeF is a DC/DC converter in TSMC 55uLPeF, flexible and readily re-targetable toward any sub micron ...
1194
3.0
Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
Foundry sponsored - Two Port Register File compiler - TSMC 55 nm uLPeFlash - Memory optimized for high density and low power - Dual Voltage - compiler...
1195
3.0
Two Port Register File compiler - Memory optimized fore high density and high speed - compiler range up to 320 k
Foundry sponsored - Two Port Register File compiler - TSMC 55 nm HV - Memory optimized fore high density and high speed - compiler range up to 320 k...
1196
3.0
Two Port Register File compiler - Memory optimized fore high density and high speed - compiler range up to 320 k
Foundry sponsored - Two Port Register File compiler - TSMC 55 nm HV - Memory optimized fore high density and high speed - compiler range up to 320 k...
1197
2.2581
8-Channel 12-Bit Low Power and Small Area SAR ADC
The IST_LSADC01 is a 8-Channel 12-Bit Low Power and Small Area SAR ADC. It can be used for voltage sensor readout application. It also can be combined...
1198
2.2581
7-Channel 22-Bit high performance and Low Power ADC
The IST_HPADC04 is a 7-Channel 22-Bit high performance and Low Power ADC. It can be used for power meter measurement application. PGA Buffers are embe...
1199
2.2581
2-Channel ADC and 1-Channel DAC
The IST_CODEC01_U55LPV33 IP includes 2-Channel ADC and 1-Channel DAC....
1200
2.2581
2-Channel Stereo ADC and 2-Channel Stereo DAC
The IST_CODEC01 IP includes 2-Channel Stereo ADC with Differential Mic-Phone Inputs and 2-Channel Stereo DAC with Single-Ended Line-Out Support....