True Circuits, Inc. IP Cores

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501

1.0

TSMC CLN28HPM 28nm Clock Generator PLL - 700MHz-3500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

502

1.0

TSMC CLN28HPM 28nm DDR DLL - 150MHz-750MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

503

1.0

TSMC CLN28HPM 28nm DDR DLL - 200MHz-1000MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

504

1.0

TSMC CLN28HPM 28nm DDR DLL - 316MHz-1580MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

505

1.0

TSMC CLN28HPM 28nm Deskew PLL - 175MHz-875MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

506

1.0

TSMC CLN28HPM 28nm Deskew PLL - 350MHz-1750MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

507

1.0

TSMC CLN28HPM 28nm Deskew PLL - 700MHz-3500MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

508

1.0

TSMC CLN28HPM 28nm General Purpose PLL - 350MHz-1750MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

509

1.0

TSMC CLN28HPM 28nm Multi Phase DLL - 175MHz-875MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

510

1.0

TSMC CLN28HPM 28nm Multi Phase DLL - 350MHz-1750MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

511

1.0

TSMC CLN28HPM 28nm Multi Phase DLL - 700MHz-3500MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

512

1.0

TSMC CLN28HPM 28nm Spread Spectrum PLL - 150MHz-750MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

513

1.0

TSMC CLN28HPM 28nm Spread Spectrum PLL - 300MHz-1500MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

514

1.0

TSMC CLN28HPM 28nm Spread Spectrum PLL - 600MHz-3000MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

515

1.0

TSMC CLN28LP 28nm Clock Generator PLL - 160MHz-800MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

516

1.0

TSMC CLN28LP 28nm Clock Generator PLL - 320MHz-1600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

517

1.0

TSMC CLN28LP 28nm Clock Generator PLL - 80MHz-400MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

518

1.0

TSMC CLN28LP 28nm DDR DLL - 120MHz-600MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

519

1.0

TSMC CLN28LP 28nm DDR DLL - 189MHz-945MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

520

1.0

TSMC CLN28LP 28nm DDR DLL - 90MHz-450MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

521

1.0

TSMC CLN28LP 28nm Deskew PLL - 160MHz-800MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

522

1.0

TSMC CLN28LP 28nm Deskew PLL - 320MHz-1600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

523

1.0

TSMC CLN28LP 28nm Deskew PLL - 80MHz-400MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

524

1.0

TSMC CLN28LP 28nm General Purpose PLL - 160MHz-800MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

525

1.0

TSMC CLN28LP 28nm Multi Phase DLL - 160MHz-800MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

526

1.0

TSMC CLN28LP 28nm Multi Phase DLL - 320MHz-1600MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

527

1.0

TSMC CLN28LP 28nm Multi Phase DLL - 80MHz-400MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

528

1.0

TSMC CLN28LP 28nm Spread Spectrum PLL - 140MHz-700MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

529

1.0

TSMC CLN28LP 28nm Spread Spectrum PLL - 280MHz-1400MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

530

1.0

TSMC CLN28LP 28nm Spread Spectrum PLL - 70MHz-350MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

531

1.0

TSMC CLN40G 40nm Clock Generator PLL - 170MHz-850MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

532

1.0

TSMC CLN40G 40nm Clock Generator PLL - 340MHz-1700MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

533

1.0

TSMC CLN40G 40nm Clock Generator PLL - 680MHz-3400MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

534

1.0

TSMC CLN40G 40nm DDR DLL - 150MHz-750MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

535

1.0

TSMC CLN40G 40nm DDR DLL - 200MHz-1000MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

536

1.0

TSMC CLN40G 40nm DDR DLL - 316MHz-1580MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

537

1.0

TSMC CLN40G 40nm Deskew PLL - 170MHz-850MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

538

1.0

TSMC CLN40G 40nm Deskew PLL - 340MHz-1700MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

539

1.0

TSMC CLN40G 40nm Deskew PLL - 680MHz-3400MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

540

1.0

TSMC CLN40G 40nm General Purpose PLL - 340MHz-1700MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

541

1.0

TSMC CLN40G 40nm Multi Phase DLL - 170MHz-850MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

542

1.0

TSMC CLN40G 40nm Multi Phase DLL - 340MHz-1700MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

543

1.0

TSMC CLN40G 40nm Multi Phase DLL - 680MHz-3400MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

544

1.0

TSMC CLN40G 40nm Spread Spectrum PLL - 150MHz-750MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

545

1.0

TSMC CLN40G 40nm Spread Spectrum PLL - 300MHz-1500MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

546

1.0

TSMC CLN40G 40nm Spread Spectrum PLL - 600MHz-3000MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

547

1.0

TSMC CLN40LP 40nm Clock Generator PLL - 150MHz-750MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

548

1.0

TSMC CLN40LP 40nm Clock Generator PLL - 300MHz-1500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

549

1.0

TSMC CLN40LP 40nm Clock Generator PLL - 75MHz-375MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

550

1.0

TSMC CLN40LP 40nm DDR DLL - 112MHz-560MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

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