Design & Reuse
5454 IP
1951
0.0
TSMC CLN4PLVT 4nm DDR DLL - 568MHz-2840MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
1952
0.0
TSMC CLN4PLVT 4nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individ...
1953
0.0
TSMC CLN4PLVT 4nm DDR4 PHY - 4266Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individ...
1954
0.0
TSMC CLN4PLVT 4nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individ...
1955
0.0
TSMC CLN4PLVT 4nm Deskew PLL - 1200MHz-6000MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1956
0.0
TSMC CLN4PLVT 4nm Deskew PLL - 300MHz-1500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1957
0.0
TSMC CLN4PLVT 4nm Deskew PLL - 600MHz-3000MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1958
0.0
TSMC CLN4PLVT 4nm General Purpose PLL - 600MHz-3000MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
1959
0.0
TSMC CLN4PLVT 4nm LPDDR3 PHY - 2133Mbps
The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin indiv...
1960
0.0
TSMC CLN4PLVT 4nm LPDDR4 PHY - 4266Mbps
The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin indiv...
1961
0.0
TSMC CLN4PLVT 4nm LPDDR5 PHY - 6400Mbps
The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin indiv...
1962
0.0
TSMC CLN4PLVT 4nm Multi Phase DLL - 1200MHz-6000MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
1963
0.0
TSMC CLN4PLVT 4nm Multi Phase DLL - 300MHz-1500MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
1964
0.0
TSMC CLN4PLVT 4nm Multi Phase DLL - 600MHz-3000MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
1965
0.0
TSMC CLN4PLVT 4nm Spread Spectrum PLL - 1050MHz-5250MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1966
0.0
TSMC CLN4PLVT 4nm Spread Spectrum PLL - 262MHz-1310MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1967
0.0
TSMC CLN4PLVT 4nm Spread Spectrum PLL - 524MHz-2620MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1968
0.0
TSMC CLN4PLVT 4nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
1969
0.0
TSMC CLN55GP 55nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
1970
0.0
TSMC CLN55LP 55nm IoT PLL - 30MHz-300MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication ...
1971
0.0
TSMC CLN55LP 55nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
1972
0.0
TSMC CLN5P 5nm Clock Generator PLL - 200MHz-1000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1973
0.0
TSMC CLN5P 5nm Clock Generator PLL - 400MHz-2000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1974
0.0
TSMC CLN5P 5nm Clock Generator PLL - 800MHz-4000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1975
0.0
TSMC CLN5P 5nm DDR DLL - 188MHz-940MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
1976
0.0
TSMC CLN5P 5nm DDR DLL - 250MHz-1250MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
1977
0.0
TSMC CLN5P 5nm DDR DLL - 395MHz-1975MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
1978
0.0
TSMC CLN5P 5nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individ...
1979
0.0
TSMC CLN5P 5nm DDR4 PHY - 4266Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individ...
1980
0.0
TSMC CLN5P 5nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individ...
1981
0.0
TSMC CLN5P 5nm Deskew PLL - 200MHz-1000MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1982
0.0
TSMC CLN5P 5nm Deskew PLL - 400MHz-2000MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1983
0.0
TSMC CLN5P 5nm Deskew PLL - 800MHz-4000MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1984
0.0
TSMC CLN5P 5nm General Purpose PLL - 400MHz-2000MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
1985
0.0
TSMC CLN5P 5nm IoT PLL - 30MHz-1000MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication ...
1986
0.0
TSMC CLN5P 5nm LPDDR3 PHY - 2133Mbps
The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin indiv...
1987
0.0
TSMC CLN5P 5nm LPDDR4 PHY - 4266Mbps
The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin indiv...
1988
0.0
TSMC CLN5P 5nm LPDDR5 PHY - 6400Mbps
The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin indiv...
1989
0.0
TSMC CLN5P 5nm Multi Phase DLL - 200MHz-1000MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
1990
0.0
TSMC CLN5P 5nm Multi Phase DLL - 400MHz-2000MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
1991
0.0
TSMC CLN5P 5nm Multi Phase DLL - 800MHz-4000MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
1992
0.0
TSMC CLN5P 5nm Spread Spectrum PLL - 175MHz-875MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1993
0.0
TSMC CLN5P 5nm Spread Spectrum PLL - 350MHz-1750MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1994
0.0
TSMC CLN5P 5nm Spread Spectrum PLL - 700MHz-3500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1995
0.0
TSMC CLN5P 5nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
1996
0.0
TSMC CLN5PLVT 5nm Clock Generator PLL - 1200MHz-6000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1997
0.0
TSMC CLN5PLVT 5nm Clock Generator PLL - 300MHz-1500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1998
0.0
TSMC CLN5PLVT 5nm Clock Generator PLL - 600MHz-3000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1999
0.0
TSMC CLN5PLVT 5nm DDR DLL - 270MHz-1350MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2000
0.0
TSMC CLN5PLVT 5nm DDR DLL - 360MHz-1800MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...