True Circuits, Inc. IP Cores

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301

1.0

UMC L80G 80nm Spread Spectrum PLL - 480MHz-2400MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

302

1.0

UMC L80GOD 80nm Clock Generator PLL - 150MHz-750MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

303

1.0

UMC L80GOD 80nm Clock Generator PLL - 300MHz-1500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

304

1.0

UMC L80GOD 80nm Clock Generator PLL - 600MHz-3000MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

305

1.0

UMC L80GOD 80nm DDR DLL - 150MHz-750MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

306

1.0

UMC L80GOD 80nm DDR DLL - 200MHz-1000MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

307

1.0

UMC L80GOD 80nm Deskew PLL - 150MHz-750MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

308

1.0

UMC L80GOD 80nm Deskew PLL - 300MHz-1500MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

309

1.0

UMC L80GOD 80nm Deskew PLL - 600MHz-3000MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

310

1.0

UMC L80GOD 80nm Spread Spectrum PLL - 150MHz-750MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

311

1.0

UMC L80GOD 80nm Spread Spectrum PLL - 300MHz-1500MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

312

1.0

UMC L80GOD 80nm Spread Spectrum PLL - 600MHz-3000MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

313

1.0

UMC L90G 90nm Clock Generator PLL - 180MHz-900MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

314

1.0

UMC L90G 90nm Clock Generator PLL - 360MHz-1800MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

315

1.0

UMC L90G 90nm Clock Generator PLL - 90MHz-450MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

316

1.0

UMC L90G 90nm DDR DLL - 108MHz-540MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

317

1.0

UMC L90G 90nm DDR DLL - 144MHz-720MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

318

1.0

UMC L90G 90nm Deskew PLL - 180MHz-900MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

319

1.0

UMC L90G 90nm Deskew PLL - 360MHz-1800MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

320

1.0

UMC L90G 90nm Deskew PLL - 90MHz-450MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

321

1.0

UMC L90G 90nm Spread Spectrum PLL - 180MHz-900MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

322

1.0

UMC L90G 90nm Spread Spectrum PLL - 360MHz-1800MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

323

1.0

UMC L90G 90nm Spread Spectrum PLL - 90MHz-450MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

324

1.0

UMC L90GOD 90nm Clock Generator PLL - 125MHz-625MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

325

1.0

UMC L90GOD 90nm Clock Generator PLL - 250MHz-1250MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

326

1.0

UMC L90GOD 90nm Clock Generator PLL - 500MHz-2500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

327

1.0

UMC L90GOD 90nm DDR DLL - 144MHz-720MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

328

1.0

UMC L90GOD 90nm DDR DLL - 192MHz-960MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

329

1.0

UMC L90GOD 90nm Deskew PLL - 125MHz-625MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

330

1.0

UMC L90GOD 90nm Deskew PLL - 250MHz-1250MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

331

1.0

UMC L90GOD 90nm Deskew PLL - 500MHz-2500MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

332

1.0

UMC L90GOD 90nm Spread Spectrum PLL - 125MHz-625MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

333

1.0

UMC L90GOD 90nm Spread Spectrum PLL - 250MHz-1250MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

334

1.0

UMC L90GOD 90nm Spread Spectrum PLL - 500MHz-2500MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

335

1.0

UMC L90SP 90nm Clock Generator PLL - 120MHz-600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

336

1.0

UMC L90SP 90nm Clock Generator PLL - 240MHz-1200MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

337

1.0

UMC L90SP 90nm Clock Generator PLL - 60MHz-300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

338

1.0

UMC L90SP 90nm DDR DLL - 60MHz-300MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

339

1.0

UMC L90SP 90nm DDR DLL - 80MHz-400MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

340

1.0

UMC L90SP 90nm Deskew PLL - 120MHz-600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

341

1.0

UMC L90SP 90nm Deskew PLL - 240MHz-1200MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

342

1.0

UMC L90SP 90nm Deskew PLL - 60MHz-300MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

343

1.0

UMC L90SP 90nm Spread Spectrum PLL - 120MHz-600MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

344

1.0

UMC L90SP 90nm Spread Spectrum PLL - 240MHz-1200MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

345

1.0

UMC L90SP 90nm Spread Spectrum PLL - 60MHz-300MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

346

1.0

TSMC CL013G 130nm Clock Generator PLL - 136MHz-680MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

347

1.0

TSMC CL013G 130nm Clock Generator PLL - 272MHz-1360MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

348

1.0

TSMC CL013G 130nm Clock Generator PLL - 68MHz-340MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

349

1.0

TSMC CL013G 130nm DDR DLL - 107MHz-535MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

350

1.0

TSMC CL013G 130nm DDR DLL - 51MHz-255MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

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