Design & Reuse
Catalog of SIP Cores
System on Chip design resources
1632 IP
1001
2.2581
Auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application
The IST-RTC01 IP is an auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application. It embeds low power LDO, 32K XOSC, POR,...
1002
2.2581
Auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application
The IST-RTC02ANA Analog IP is a auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application. It embeds low power LDO, 32K O...
1003
2.2581
Auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application
The IST-RTC02ANA Analog IP is an auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application. It embeds low power LDO, 32K ...
1004
2.2581
Auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application
The IST-RTC01ANA Analog IP is a auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application. It embeds low power LDO, 32K O...
1005
2.2581
Auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application
The IST-RTC01ANA Analog IP is a auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application. It embeds low power LDO, 32K O...
1006
2.2581
Auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application
The IST-RTC01ANA Analog IP is a auxiliary block for the low-cost, extremely accurate real-time clock (RTC) application. It embeds low power LDO, 32K X...
1007
200.0
Post-Quantum Cryptography - xQlave® PQC ML-KEM (Kyber)
In a world where advances in quantum computing threaten traditional cryptographic systems, Xiphera’s xQlave® ML-KEM (Kyber) Key Encapsulation Mechanis...
1008
130.0
LPDDR6, LPDDR5X Combo PHY & Controller
INNOSILICON™ introduces its LPDDR6/5X PHY and Controller IP, purpose-built for the AI era’s high-performance chip design needs. This solution is fully...
1009
105.0
CME IoT platform
Sensor-Mate (sensing node)Long distance wireless communication (920MHz)Sensor-Gateway (Aggregator)920MHz wireless module (CM Engineering proprietary)G...
1010
100.0
MACsec - Extreme-speed - Security Protocol
MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera's comprehensive MACsec solution portfolio safeguards th...
1011
100.0
PCIe 5.0 PHY & Controller
The Innosilicon Gen1/2/3/4/5 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, h...
1012
100.0
Post-Quantum Cryptography - nQrux® Quantum Secure Boot
nQrux® Quantum Secure Boot enhances system security by enabling quantum-secure authenticated boot, crucial for verifying the authenticity and integrit...
1013
100.0
Post-Quantum Cryptography - xQlave® PQC ML-DSA (Dilithium)
The xQlave® ML-DSA (Dilithium) Digital Signature Algorithm IP core secures critical infrastructures and operations against the threat of quantum compu...
1014
100.0
LPDDR5X, LPDDR5, LPDDR4X, LPDDR4 Combo PHY & Controller
The INNOSILICON™ LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller. It is fully compliant with the JEDEC standard. Optimized for low-power a...
1015
80.0
GDDR7 PHY & Controller
The INNOSILICON™ GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode. In PAM3 mode, each b...
1016
60.0
UCIe Chiplet PHY & Controller
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
1017
51.0
TLS 1.3 - Security Protocol
Transport Layer Security (TLS) is a cryptographic protocol used for building a secure connection between a client and a server over the Internet. A ha...
1018
51.0
True Random Number Generator (TRNG)
The TRNG IP core establishes a benchmark for hardware-based security in cryptographic systems, by generating high-entropy, true random numbers essenti...
1019
50.0
AES - GCM - Extreme-speed variant
XIP1113E is a an extreme-speed IP core implementing the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). AES-GCM is a widely used cryp...
1020
50.0
IPsec - Security Protocol
IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s IPsec core enhances secure...
1021
48.0
nQrux® Crypto Module
Xiphera’s nQrux® Crypto Module IP core provides a comprehensive security platform that allows for customisation of top-notch cryptographic services, s...
1022
43.0
Elliptic Curve Cryptography (ECC) Accelerator
The high-speed ECC Accelerator reaches to more than a thousand operations per second in a modern FPGA or ASIC. Furthermore, it covers all NIST P curve...
1023
25.0
HBM4, HBM3E PHY & Controller
INNOSILICON™ HBM4/3E IP is fully compliant with the JEDEC standard for HBM3E and the preliminary specification for HBM4. The IP includes a customizabl...
1024
25.0
DDR5, DDR4 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR5/4 Combo PHY s provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDR...
1025
20.0
MAXVY MIPI CSI2 Receiver IP
The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile...
1026
20.0
MAXVY MIPI DSI-2 Transmitter Interface IP
MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile dev...
1027
15.0
GDDR6X, GDDR6 Combo PHY & Controller
The INNOSILICON™ GDDR6X/6 PHY is fully compliant with the JEDEC GDDR6X/6 standard, supporting data rates of up to 20 Gbps per pin for PAM2 GDDR6 mode ...
1028
10.0
MAXVY Technologies
MAXVY is a fast growing fabless semiconductor company which is currently engaged in the fields of RTL design and Verification IP Solutions. We offe...
1029
10.0
Expanded Serial Peripheral Interface (xSPI) Slave Controller
The MAXVY's JESD251 Expanded Serial Peripheral Interface Slave controller is provides high data throughput, low signal count, and limited backward com...
1030
8.0
MAXVY Universal Chiplet Interconnect Express (UCIe) Verification IP
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of you...
1031
8.0
MIPI I3C Verification IP
The Maxvy's MIPI-I3C VIP provides configurable option to select I3C master/secondary master/slave based on the MIPI I3C DUT function as per user speci...
1032
5.0
DDR5 CKD 01 - Clock Driver
MAXVY DDR5CKD01 is a high-performance FPGA-proven registering clock driver designed for DDR5 CUDIMM, CSODIMM, and CAMM applications, providing relia...
1033
5.0
DDR5 Power Management IC
Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application. PMIC is used for switching and LDO regulators. PMIC-I3C I...
1034
5.0
DDR5 REGISTERING CLOCK DRIVER (RCD) IP - DDR5RCD03
The DDR5RCD03 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs. Its primary function is to buffer the Command/Address (CA) bus, chip sele...
1035
5.0
DDR5 Serial Presence Detect (SPD5) Hub Interface
The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), fro...
1036
5.0
DDR5 Temperature Sensor - TS5111 and TS5110
he TS5111 and TS5110 device incorporate thermal sensing capability which is controlled and read over two wire bus. These device operate on I2C and I3C...
1037
5.0
MIPI I3C Master RISC-V based subsystem
RISC-V based MAXVY MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a ...
1038
5.0
MIPI-I3C COMBINED IP HOST/TARGET IP
The MAXVY MIPI I3C Controller IP (Host/Target) is a high-performance, standards-compliant solution for efficient multi-sensor integration in mobile,...
1039
3.0
Pseudorandom Number Generator (PRNG) - Balanced variant
The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...
1040
3.0
Pseudorandom Number Generator (PRNG) - High-speed variant
The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...
1041
2.0
HBM3, HBM3E PHY & Controller
This document describes a general layout scheme and Innosilicon HBM3/3E PHY connecting to the controller using a DFI digital interface. All interface ...
1042
2.0
MIPI A-PHY Verification IP
MIPI A-PHY v1.0 is a physical layer communication protocol designed for automotive applications, including driver assistance, autonomous driving, and ...
1043
2.0
Innosilicon - High-Quality ASIC Customization Services
With a team of first-class experts, highly-reliable chip customization ability, and rich experience in mass production on processes from 55nm to 5nm, ...
1044
1.0
10G Multi-SerDes PHY
The Innosilicon 10G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 10Gbps within a single lane. The PHY can be configured ...
1045
1.0
12.5G Multi-SerDes PHY
The Innosilicon 12.5G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 12.5Gbps within a single lane. For this particular da...
1046
1.0
32G Multi-SerDes For PCIe5.0/USB3.x PHY
The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this datasheet, the PH...
1047
1.0
32G Multi-SerDes PHY + Controller
The INNOSILICON™ 32G Multi-SerDes PHY is a highly configurable IP solution capable of supporting data rates of up to 32 Gbps per lane. It is designed ...
1048
1.0
64G/56G SerDes
The Innosilicon 64G/56G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 56Gbps within a single lane. For this datasheet, th...
1049
1.0
25G Multi-SerDes PHY
The Innosilicon 25G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datash...
1050
1.0
HBM2E PHY&Controller
Innosilicon HBM2E PHY IP is a silicon proven product with max speed up to 3600Mbps per DQ data, HBM2E memory has 1024bit DQ, total bandwidth can be 3....