Design & Reuse
Catalog of SIP Cores
System on Chip design resources
1632 IP
1151
0.0
AES - XTS - Balanced variant
XIP1183B is a balanced IP core implementing the Advanced Encryption Standard (AES) with 256-bit key in XTS mode. AES-XTS is block-oriented cipher for...
1152
0.0
AES - XTS - High-speed variant
XIP1183H is a high-speed IP core implementing the Advanced Encryption Standard (AES) with 256-bit key in XTS mode. AES-XTS is block-oriented cipher f...
1153
0.0
DES Cryptoprocessor
This core is a fully compliant implementation of the DES encryption algorithm. Both encryption and decryption are supported. ECB, CBC and triple DES v...
1154
0.0
JESD204B Controller
JESD204B is a standardized serial interface for communication between logic devices (ASIC or FPGA) and converters (ADC or DAC). Innosilicon’s JESD204B...
1155
0.0
JESD204B PHY & Controller
JESD204B is a standardized serial interface for communication between logic devices (ASIC or FPGA) and converters (ADC or DAC). Innosilicon’s JESD204B...
1156
0.0
SGMII PHY
The Innosilicon SGMII PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the IEEE802.3 1000BAS...
1157
0.0
SHA-2 Hash Function (SHA-256) - Balanced variant
The SHA-2 IP from Xiphera is a versatile Intellectual Property (IP) core designed for SHA-256 cryptographic hash function with extended support for HM...
1158
0.0
SHA-2 Hash Function (SHA-256/512) - Compact variant
The SHA-2 IP from Xiphera is a versatile Intellectual Property (IP) core designed for SHA-256 and SHA-512 cryptographic hash functions with extended s...
1159
0.0
SHA-2 Hash Function (SHA-384) - Balanced variant
The SHA-2 IP from Xiphera is a versatile Intellectual Property (IP) core designed for SHA-384 cryptographic hash function with extended support for HM...
1160
0.0
SHA-2 Hash Function (SHA-512) - Balanced variant
The SHA-2 IP from Xiphera is a versatile Intellectual Property (IP) core designed for SHA-512 cryptographic hash function with extended support for HM...
1161
0.0
SHA-3 Hash Function - Compact variant
This IP core support SHA3-224, SHA3-256, SHA3-384, SHA3-512, and related functions such as SHAKE, cSHAKE, KMAC,TupleHash, and ParallelHash. Xiphera's...
1162
0.0
SHA-3 Hash Function - High-speed variant
This IP core support SHA3-224, SHA3-256, SHA3-384, SHA3-512, and related functions such as SHAKE, cSHAKE, KMAC,TupleHash, and ParallelHash. Xiphera's...
1163
0.0
ChaCha20-Poly1305 - Balanced variant
Xiphera's ChaCha20-Poly1305 symmetric encryption IP cores provide robust security for a wide range of applications. It combines the high-speed ChaCha2...
1164
0.0
ChaCha20-Poly1305 - High-speed variant
Xiphera's ChaCha20-Poly1305 symmetric encryption IP cores provide robust security for a wide range of applications. It combines the high-speed ChaCha2...
1165
0.0
Video Codec
Innosilicon Video Codec is 4K multi-format codec IP supporting both H.265/HEVC and H.264/AVC video formats. This IP core provides high performance enc...
1166
0.0
Video DAC
INNOSILICON™ Video DAC IP is designed for transmitting analog video signals from a video source device to a display device, which can be used to build...
1167
0.0
Video-by-One Receiver IP_16ch
This document introduces the low power Innosilicon Video-by-One (VBO) Receiver IP containing PHY and controller. Innosilicon VBO RX is designed for re...
1168
0.0
Video-by-One Transmitter IP_8ch
Innosilicon VBO TX IP is designed for transmitting video data from a video source device to a display device. It is compatible with V-By-One HS 1.4 st...
1169
0.0
High Performance Second Generation Extended MIPI CSI2 Receiver
Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth betwe...
1170
0.0
SiliConch Systems Pvt Ltd - Design and Verification services
Who we areSiliConch Systems is fab-less semiconductor company, established in 2016 having its headquarters in Bangalore, India. Where We BeganSiliC...
1171
0.0
Xiphera Hardware Security IP Solutions - Complete IP Overview
We protect your critical systems by designing security directly into hardware. At Xiphera, we specialise in designing cutting-edge, hardware-based s...
1172
0.0
MIPI C-PHY DSI RX IP
Innosilicon MIPI DSI RX IP implements the MIPI C-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...
1173
0.0
MIPI C-PHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI C-PHY protocol. The DSI link protocol specification is a part of group of...
1174
0.0
MIPI C-PHY RX PHY
The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...
1175
0.0
MIPI C-PHY TX PHY
The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...
1176
0.0
MIPI C/D-PHY CSI-2 RX IP
Innosilicon CSI-2 Receiver implements MIPI CSI-2 as well as C/D-PHY protocols. The CSI-2 link protocol specification is a part of group of communicati...
1177
0.0
MIPI C/D-PHY RX
The Innosilicon MIPI C/D-PHY RX provides D-PHY and C-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, p...
1178
0.0
MIPI C/D-PHY TX
The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...
1179
0.0
MIPI CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
1180
0.0
MIPI CSI-2 TX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
1181
0.0
MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 spec...
1182
0.0
MIPI D-PHY Combo LVDS CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2, MIPI D-PHY, and LVDS protocols. The CSI-2 link protocol specification is a part of group of communication...
1183
0.0
MIPI D-PHY Combo LVDS DSI TX IP
Innosilicon MIPI DSI Transmitter implements DSI, MIPI D-PHY, and LVDS protocol. The DSI link protocol specification is a part of group of communicatio...
1184
0.0
MIPI D-PHY CSI-2 RX IP
Innosilicon CSI-2 Receiver implements MIPI CSI-2 protocol as well as D-PHY protocol. The CSI-2 link protocol specification is a part of group of commu...
1185
0.0
MIPI D-PHY DSI 1.2G RX IP
Innosilicon MIPI DSI receiver implements the MIPI DSI as well as D-PHY protocols. The DSI link protocol specification is a part of group of communicat...
1186
0.0
MIPI D-PHY DSI 1.5G RX IP
Innosilicon MIPI DSI RX IP implements the MIPI D-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...
1187
0.0
MIPI D-PHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...
1188
0.0
MIPI D-PHY TX
The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...
1189
0.0
MIPI D-PHY TX COMBO LVDS PHY
The Innosilicon MIPI D-PHY TX combo LVDS PHY integrates a D-PHY and a LVDS in a single IP core, which provides a MIPI® high speed data plus low-power ...
1190
0.0
MIPI D-PHY TX Combo TTL PHY
The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...
1191
0.0
MIPI D-PHY_1.2G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
1192
0.0
MIPI D-PHY_1.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
1193
0.0
MIPI D-PHY_2.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
1194
0.0
MIPI D-PHY_4.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
1195
0.0
MIPI DPHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...
1196
0.0
MIPI DPHY1.2 RX (support combo TTL, LVDS, HiSPI)
The Innosilicon MIPI D-PHY IP provides D-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, plus a MIPI® ...
1197
0.0
MIPI DPHY2.0/CPHY1.1 TX (support combo TTL, LVDS, HiSPI)
The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...
1198
0.0
MIPI DSI-2 DSC RX IP
Innosilicon MIPI DSI-2 DSC RX IP implements the MIPI C/D-PHY as well as MIPI DSI-2 protocols and contains the DSC (Display Stream Compression) algorit...
1199
0.0
MIPI M-PHY
INNOSILICON™ M-PHY IP implements the MIPI M-PHY protocol V4.1. The M-PHY protocol specification is a part of a group of communication protocols define...
1200
0.0
RISC V - CORE DEVELOPMENT
RISC-V (pronounced risk-five ) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015...