Design & Reuse
Catalog of SIP Cores
System on Chip design resources
1632 IP
1201
0.0
Discrete Cosine Transform OL_DCT
This core can perform the two dimensional Discrete Cosine Transform (DCT) and its inverse (IDCT) on an 8x8 block of samples. The simple, fully synchro...
1202
0.0
NIST P-224/P-256/P-384/P521 ECDH and ECDSA
The NIST P-224/P-256/P-384/P-521 ECDH and ECDSA can be used for elliptic curve key generation, computation of Diffie-Hellman shared secrets as well as...
1203
0.0
DLL
The INNOSILICON™ Delay-Locked Loop (DLL) PHY is a mix-signal circuit used in low-power and high-speed applications to align and synchronize clock sign...
1204
0.0
PLL
INNOSILICON™ PLL IP is a high-speed, low-jitter frequency synthesizer, developed to reduce time-to-market, risk, and design cost. It can generate a st...
1205
0.0
VLSI Plus - ISP Design Services and Engineering Services
VLSI Plus team of image processing professional, experienced in the definition and efficient VLSI implementation of high image quality ISP (Image Si...
1206
0.0
OL_H264E-CFS HDTV H.264/AVC Video Encoder with Compressed Frame Store
The OL_H264E-CFS core is a hardware implementation of the H.264 video compression algorithm. The core accepts up to the highest resolution HDTV video ...
1207
0.0
eMMC/SD/SDIO PHY & Controller
INNOSILICON™ eMMC/SD/SDIO Combo IP is a comprehensive solution designed to support high-performance storage and I/O connectivity for a wide range of a...
1208
0.0
Analog Mixed-Signal and RFIC design service
Engage with customer in all stages of design from feasibility study, architecture modeling and sim, circuit and layout design, to evaluation. RF IC...
1209
0.0
ONFI
INNOSILICON™ ONFI IP provides a connectivity solutions for ICs requiring access to ONFI-compatible NAND Flash devices. Optimized for low-power and hig...
1210
0.0
INNOLINK Chiplet PHY&Controller
Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chi...
1211
0.0
INNOLINK-B Controller
The INNOLINK Controller (ILC) combined with INNOLINK PHY is a complete solution for high speed data communication between dies or chips. INNOLIN, GDDR...
1212
0.0
INNOLINK-B PHY
Innosilicon can provide different Die2Die solution for customer depend on package type, Following is Innosilicon Die2Die IP family: Innolink-A, Serde...
1213
0.0
INNOLINK-C Controller
The INNOLINK-C Controller (hereinafter referred to as “ILC”) combined with INNOLINK-C PHY is a complete solution for high-speed data communication bet...
1214
0.0
INNOLINK-C PHY
Innosilicon can provide different Die-to-Die and Chip-to-Chip solutions for customer according to package types. The followings are Innosilicon Die-to...
1215
0.0
Innovative Ultra-High-Speed Chiplet Solution
Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chip...
1216
0.0
Low Power Mono Audio CODEC_1ADC1DAC
Innosilicon Audio Codec IP is a low power, high resolution, mono CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and po...
1217
0.0
Low Power Stereo Audio CODEC
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
1218
0.0
Low Power Stereo Audio CODEC_2ADC1DAC
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
1219
0.0
Low Power Stereo Audio CODEC_2ADC2DAC
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
1220
0.0
Low Power Stereo Audio CODEC_4ADC4DAC
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
1221
0.0
Low Power Stereo Audio CODEC_80db
Innosilicon Codec is a low power, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amplifier are integr...
1222
0.0
Low Power Stereo Audio CODEC_90dB
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
1223
0.0
Power-On-Reset IP
INNOSILICON™ Power-On-Reset (POR) IP provides reliable reset functions for a variety of applications. It is powered by an analog supply and monitors b...
1224
0.0
DP/eDP PHY + Controller
INNOSILICON™ DP/eDP IP is designed for transmitting or receiving video and audio signals between the video source devices and display devices. It is f...
1225
0.0
DP1.1 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
1226
0.0
DP1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
1227
0.0
DP1.2 Transmitter PHY
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
1228
0.0
DP1.2 Transmitter PHY_40nm
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
1229
0.0
DP1.4 Receiver Controller
This document describes the low power Innosilicon DP 1.4 Receiver controller, which is fully compliant with DP 1.4 specification and eDP 1.4 standard....
1230
0.0
DP1.4 TX PHY
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...
1231
0.0
LPDDR2 PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR2 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devi...
1232
0.0
LPDDR3/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR3/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SD...
1233
0.0
LPDDR3/2/DDR3/3L Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR2/3/DDR3/3L COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compa...
1234
0.0
LPDDR3/2/DDR3/3L/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR3/2/DDR3/3L/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC com...
1235
0.0
LPDDR4X, LPDDR4, DDR4, LPDDR3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR4/4X/DDR4/LPDDR3 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compat...
1236
0.0
LPDDR4X/4/3/DDR4/3/3L PHY + Controller
INNOSILICON™ LPDDR4X/4/3/DDR4/3/3L Combo IP is a customizable Mixed-Signal DDR memory interface suite. The Combo IP provides turnkey physical interfac...
1237
0.0
nQrux - Hardware Trust Engines
Xiphera's nQrux™ family of Hardware Trust Engines offers ready-to-implement security modules for various security architectures. The nQrux&t...
1238
0.0
MRDIMM DDR5 & DDR5/4 PHY & Controller
INNOSILICON™ DDR5 IP includes the MRDIMM DDR5 PHY and DDR5/4 Combo PHY and corresponding controllers for ICs requiring access to JEDEC compatible SDRA...
1239
0.0
Process/Voltage/ Temperature Sensor
INNOSILICON™ PVT Sensor IP is designed for on-chip monitoring of processes, voltage, and temperature variations. It is a critical component in modern ...
1240
0.0
RSA Signature Verification
The RSA Signature Verification from Xiphera is a very compact Intellectual Property (IP) core designed for RSA (Rivest-Shamir-Adleman) signature verif...
1241
0.0
Ascon
Xiphera's Ascon symmetric encryption IP cores provide robust security for a wide range of applications. It is, as a lightweight encryption algorithm, ...
1242
0.0
HSIC PHY
The Innosilicon HSIC PHY is fully compliant with the High-Speed Inter-Chip Supplement to the USB 2.0 Specification. By stripping off all the legacy US...
1243
0.0
PSRAM PHY
The INNOSILICON DDR IPTM Mixed-Signal PSRAM PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible PSRAM devic...
1244
0.0
PSRAM/RPC PHY & Controller
INNOSILICON™ PSRAM IP consists of a configurable PHY and RPC PHY and a controller. It provides the physical interface solutions for ICs requiring acce...
1245
0.0
Standalone IPsec
IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s IPsec IP core enhances sec...
1246
0.0
LTE UE PHY layer
The PHY baseband covers all Synchronization Signals, downlink and uplink Physical Channels, libraries, algorithms integrated with cross-functional log...
1247
0.0
LTE UE Protocol Stack HW (Arm, Cortex A8)
Mymo offers 3GPP LTE Release-9 UE FDD and TDD UE Protocol Stack on Arm hardware . The Integrated solution of MAC-RLC-PDCP-RRC-NAS-TCP-IP with several ...
1248
0.0
LTE UE Protocol Stack Software
Mymo offers 3GPP LTE Release-9 UE FDD and TDD UE Protocol Stack software. The software is in ANSI C ported at RT-Linux kernel level ideally suited for...
1249
0.0
Successive Approximation ADC_2M10b
Innosilicon SARADC IP is a small-sized, low power analog to digital converter with input channels. The converter is a charge-redistribution successive...
1250
0.0
Successive Approximation ADC_2M12b
Innosilicon SAR-ADC IP is a small-size, low power analog to digital converter. The converter is a charge-redistribution successive approximation ADC. ...