Design & Reuse
Catalog of SIP Cores
System on Chip design resources
5452 IP
901
10.0
Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)
The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...
902
10.0
Differential Clock Receiver - TSMC CLN2P
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
903
10.0
Differential Clock Receiver - TSMC CLN3A
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
904
10.0
Differential Clock Receiver - TSMC CLN3E
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
905
10.0
Differential Clock Receiver to CML - TSMC CLN2P
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
906
10.0
Differential Clock Receiver to CML - TSMC CLN3A
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
907
10.0
Differential Clock Receiver to CML - TSMC CLN3E
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
908
10.0
Differential Clock Receiver to CML - TSMC CLN6FF
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
909
10.0
Differential Clock Reciever - TSMC CLN3P
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
910
10.0
Differential Clock Reciever to CML - TSMC CLN3P
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
911
10.0
Differential Output Buffer - TSMC CLN3P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a...
912
10.0
Differential Output Buffer - TSMC 6FF
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
913
10.0
Differential Output Buffer - TSMC CLN3E
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
914
10.0
Differential Output Buffer - TSMC CLN3P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
915
10.0
Differential Output Buffer - TSMC CLN4P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
916
10.0
Differential Output Buffer - TSMC N5
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
917
10.0
Differential Output Driver - TSMC CLN2P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
918
10.0
Differential Receiver - TSMC 7FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
919
10.0
Differential Signal Receiver - TSMC 6FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
920
10.0
Differential Signal Receiver - TSMC N5
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
921
10.0
High Performance 1-22.5G PCIe4/SAS4 PHY - TSMC 16FFC
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
922
10.0
High Performance 20GHz C2C PLL - TSMC CLN3A
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
923
10.0
High Performance 20GHz C2C PLL - TSMC CLN3E
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
924
10.0
High Performance 20GHz C2C PLL - TSMC CLN6FF
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
925
10.0
High Performance 20GHz PLL - TSMC CLN4P
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
926
10.0
High Performance 20GHz PLL - TSMC CLN5A
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
927
10.0
High Precision Temp Sensor - TSMC CLN2P
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
928
10.0
High Precision Temp Sensor - TSMC CLN3A
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
929
10.0
High Precision Temp Sensor - TSMC CLN3E
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
930
10.0
High Precision Temp Sensor - TSMC CLN5A
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
931
10.0
High Speed 20GHz PLL - TSMC CLN6FF
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
932
10.0
High Speed PLL - TSMC N4P
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
933
10.0
High Speed PLL - TSMC N5
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
934
10.0
High Speed PLL - TSMC N5A
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
935
10.0
High Speed PLL - TSMC N5A
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
936
10.0
High Speed PLL CML to Complementary - TSMC CLN3P
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
937
10.0
TileLink Target
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. Ti...
938
10.0
LIN Bus Master/Slave Controller Core
Implements a communication controller that transmits and receives complete Local Interconnect Network (LIN) frames to perform serial communication acc...
939
10.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
940
10.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, N7) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
941
10.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
942
10.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A, N3A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
943
10.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N5A, N3A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
944
10.0
MIPI D-PHY TSMC 130nm
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
945
10.0
MIPI D-PHY TSMC 28nm HPC+ @ 2.5Ghz
The Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Inte...
946
10.0
MIPI D-PHY Tx-Only 2 Lanes in TSMC (16nm, N7) for Automotive
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
947
10.0
MIPI D-PHY Tx-Only 4 Lanes in TSMC (16nm, N7) for Automotive
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
948
10.0
MIPI DSI-2 Transmit Controller v1.0
The Arasan DSI-2 Device Controller IP is designed to provide MIPI DSI-2 1.0 compliant high speed serial connectivity for mobile host processors using ...
949
10.0
MIPI I3C Basic Secondary Controller
The I3C-SC core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Secondary Controller core compliant with the latest MIPI I3C Basi...
950
10.0
MIPI I3C PHY I/O
Arasan’s MIPI I3CⓇ PHY I/O IP, in compliance with MIPI I3CⓇ specifications v1.1. Arasan’s MIPI I3CⓇ PHY IP is part of Arasan’s Total IP Solution for M...