VinChip Systems Inc. IP Cores

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1951

1.0

UMC L130HS 130nm Deskew PLL - 80MHz-400MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1952

1.0

UMC L130HS 130nm Spread Spectrum PLL - 160MHz-800MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1953

1.0

UMC L130HS 130nm Spread Spectrum PLL - 320MHz-1600MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1954

1.0

UMC L130HS 130nm Spread Spectrum PLL - 80MHz-400MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1955

1.0

UMC L130LL 130nm Clock Generator PLL - 120MHz-600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1956

1.0

UMC L130LL 130nm Clock Generator PLL - 30MHz-150MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1957

1.0

UMC L130LL 130nm Clock Generator PLL - 60MHz-300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1958

1.0

UMC L130LL 130nm DDR DLL - 24MHz-120MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1959

1.0

UMC L130LL 130nm DDR DLL - 32MHz-160MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1960

1.0

UMC L130LL 130nm Deskew PLL - 120MHz-600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1961

1.0

UMC L130LL 130nm Deskew PLL - 30MHz-150MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1962

1.0

UMC L130LL 130nm Deskew PLL - 60MHz-300MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1963

1.0

UMC L130LL 130nm Spread Spectrum PLL - 120MHz-600MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1964

1.0

UMC L130LL 130nm Spread Spectrum PLL - 30MHz-150MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1965

1.0

UMC L130LL 130nm Spread Spectrum PLL - 60MHz-300MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1966

1.0

UMC L130SP 130nm Clock Generator PLL - 118MHz-590MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1967

1.0

UMC L130SP 130nm Clock Generator PLL - 236MHz-1180MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1968

1.0

UMC L130SP 130nm Clock Generator PLL - 59MHz-295MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1969

1.0

UMC L130SP 130nm DDR DLL - 57MHz-285MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1970

1.0

UMC L130SP 130nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1971

1.0

UMC L130SP 130nm Deskew PLL - 118MHz-590MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1972

1.0

UMC L130SP 130nm Deskew PLL - 236MHz-1180MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1973

1.0

UMC L130SP 130nm Deskew PLL - 59MHz-295MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1974

1.0

UMC L130SP 130nm Spread Spectrum PLL - 118MHz-590MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1975

1.0

UMC L130SP 130nm Spread Spectrum PLL - 236MHz-1180MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1976

1.0

UMC L130SP 130nm Spread Spectrum PLL - 59MHz-295MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1977

1.0

UMC L150HS 150nm Clock Generator PLL - 140MHz-700MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1978

1.0

UMC L150HS 150nm Clock Generator PLL - 280MHz-1400MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1979

1.0

UMC L150HS 150nm Clock Generator PLL - 70MHz-350MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1980

1.0

UMC L150HS 150nm DDR DLL - 57MHz-285MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1981

1.0

UMC L150HS 150nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1982

1.0

UMC L150HS 150nm Deskew PLL - 140MHz-700MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1983

1.0

UMC L150HS 150nm Deskew PLL - 280MHz-1400MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1984

1.0

UMC L150HS 150nm Deskew PLL - 70MHz-350MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1985

1.0

UMC L150HS 150nm Spread Spectrum PLL - 140MHz-700MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1986

1.0

UMC L150HS 150nm Spread Spectrum PLL - 280MHz-1400MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1987

1.0

UMC L150HS 150nm Spread Spectrum PLL - 70MHz-350MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1988

1.0

UMC L180G 180nm Clock Generator PLL - 100MHz-500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1989

1.0

UMC L180G 180nm Clock Generator PLL - 200MHz-1000MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1990

1.0

UMC L180G 180nm Clock Generator PLL - 50MHz-250MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1991

1.0

UMC L180G 180nm DDR DLL - 42MHz-210MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1992

1.0

UMC L180G 180nm DDR DLL - 56MHz-280MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1993

1.0

UMC L180G 180nm Deskew PLL - 100MHz-500MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1994

1.0

UMC L180G 180nm Deskew PLL - 200MHz-1000MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1995

1.0

UMC L180G 180nm Deskew PLL - 50MHz-250MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1996

1.0

UMC L180G 180nm Spread Spectrum PLL - 100MHz-500MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1997

1.0

UMC L180G 180nm Spread Spectrum PLL - 200MHz-1000MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1998

1.0

UMC L180G 180nm Spread Spectrum PLL - 50MHz-250MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1999

1.0

UMC L55SP 55nm Clock Generator PLL - 130MHz-650MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2000

1.0

UMC L55SP 55nm Clock Generator PLL - 260MHz-1300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

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