Design & Reuse
5449 IP
3251
0.0
VC Verification IP for MIPI DSI
Synopsys® Verification IP (VIP) for UCIe provides a comprehensive set of protocol, multi-die, methodology, verification, and productivity features ena...
3252
0.0
VC Verification IP for MIPI DSI
Synopsys VC Verification IP for MIPI Display Serial Interface (DSI) provides a comprehensive set of protocol, methodology, verification and productivi...
3253
0.0
VC Verification IP for MIPI M-PHY
Synopsys VC Verification IP for MIPI M-PHY provides a comprehensive set of protocol, methodology, verification and productivity features, enabling use...
3254
0.0
VC Verification IP for NVMe
Synopsys VC VIP for Non-Volatile Memory Express (NVMe) is designed to help thoroughly verify NVMe designs using both random and directed simulation....
3255
0.0
VC Verification IP for OCP
Synopsys VC Verification IP (VIP) for OCP provides a comprehensive set of protocol, methodology, verification and productivity features enabling users...
3256
0.0
VC Verification IP for PCIe
Synopsys VC Verification IP (VIP) for PCI Express (PCIe) provides a comprehensive set of protocol, methodology, verification and productivity features...
3257
0.0
VC Verification IP for SAS
Synopsys VC Verification IP (VIP) Serial SCSI (SAS) is designed to thoroughly verify your design using both random and directed simulation....
3258
0.0
VC Verification IP for SATA
Synopsys VC Verification IP (VIP) for Serial ATA (SATA) is designed to verify SATA-based designs using both random and directed simulation....
3259
0.0
VC Verification IP for SDIO
Synopsys VC Verification IP (VIP) for SDIO is a comprehensive VIP solution enabling pre-silicon functional verification of SD (Secure Digital) IO/Memo...
3260
0.0
VC Verification IP for TileLink
Synopsys® Verification IP for TileLink provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users ...
3261
0.0
VC Verification IP for UART
Synopsys VC Verification IP (VIP) for UART provides a comprehensive set of protocol, methodology, verification and productivity features, enabling use...
3262
0.0
VC Verification IP for UFS
Synopsys® VC Verification IP for the JEDEC UFS memory protocol specification provides a comprehensive set of protocol, methodology, verification and p...
3263
0.0
VC Verification IP for USB
Synopsys® VC Verification IP for USB provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to ...
3264
0.0
TCAM Compilers for Samsung (14nm, 10nm, SF5A, SF4X)
Synopsys embedded ternary content addressable memories (TCAMs) help networking designers meet the demand for wire-speed packet processing, access cont...
3265
0.0
TCAM Compilers for SMIC (28nm)
Synopsys embedded ternary content addressable memories (TCAMs) help networking designers meet the demand for wire-speed packet processing, access cont...
3266
0.0
TCAM Compilers for TSMC (65nm, 40nm, 28nm, 16nm, N7, N6, N5, N4
Synopsys embedded ternary content addressable memories (TCAMs) help networking designers meet the demand for wire-speed packet processing, access cont...
3267
0.0
Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Mem...
3268
0.0
Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Mem...
3269
0.0
ECC Core
Rambus Error Correction Coding (ECC) Core implements the standard Hamming Code based DRAM Single Error Correction (SEC) and Double Error Detection (DE...
3270
0.0
ACCUREF - Low Power Voltage and Current Reference Circuit, 0.3% Accuracy, 90 dB PSR in TSMC C130BCD
This intellectual property (IP) core generates a precise/adjustable reference voltage (VREF), as well as two sets of reference output currents using b...
3271
0.0
LCD Controller - TFT LCD Panels (AXI4 Bus)
The Digital Blocks DB9000AXI4 TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 4.0 AXI4 Protocol Interconne...
3272
0.0
BCH Error Correcting Code ECC
BCH code statistics for different `$mm` `$tt` Zero latency, low gate count, low power, asynchronous BCH Code based Error Correction FEC: T...
3273
0.0
PCI Express Verification Component
The PCI Express eVC can be used for verification of a device that supports the PCI Express standard. The eVC is compliant to PCI Express Base Specific...
3274
0.0
PCI Master/Target Interface Core
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3275
0.0
PCI to AMBA AHB Host Bridge
This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. The bridge enables high...
3276
0.0
PCI-X Verification Component
eVCs are reusable Verification Components that can be used to establish ready-made verification environment. Each eVC is capable of acting as full ver...
3277
0.0
PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
Rambus PCIe 1.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 1.1 ...
3278
0.0
PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
Rambus PCIe 2.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 ...
3279
0.0
PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
Rambus PCIe 2.1 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 Controlle...
3280
0.0
PCIe 3.0 PHY in Samsung (SF5A
The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
3281
0.0
PCIe 3.0 PHY in TSMC (28nm, 12nm, N4P)
The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
3282
0.0
PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
Rambus PCIe 3.0 with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 3.0 with AXI is...
3283
0.0
PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
Rambus PCIe 3.0 Controller is a highly configurable PCIe 3.0 interface Soft IP designed for ASIC and FPGA implementations supporting endpoint, root po...
3284
0.0
PCIe 4.0 Controller with AMBA AXI interface
Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Contr...
3285
0.0
PCIe 4.0 PHY in Samsung (8nm) for Automotive
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
3286
0.0
PCIe 4.0 PHY IP for SS 14LPU
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
3287
0.0
PCIe 4.0 SR PHY in TSMC (N3P, N2P)
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
3288
0.0
PCIe 5.0 Controller IP
The Wolley PCI Express® (PCIe®) Controller IP is a highly configurable, performance-optimized core designed for ASIC and FPGA integration. Supporting ...
3289
0.0
PCIe 5.0 Controller with AMBA AXI interface
Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controlle...
3290
0.0
PCIe 5.0 IP on Samsung SF5
The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands ...
3291
0.0
PCIe 5.0 PHY for SF5
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
3292
0.0
PCIe 5.0 PHY for TSMC N3P
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
3293
0.0
PCIe 5.0 PHY for TSMC N7
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
3294
0.0
PCIe 5.0 PHY in GlobalFoundries (12nm)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
3295
0.0
PCIe 5.0 PHY in Samsung (SF4A) for Automotive
The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands ...
3296
0.0
PCIe 5.0 PHY IP for TSMC N5
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s application...
3297
0.0
PCIe 5.0 Premium Controller with AXI bridge & Advanced HPC Features (Arm CCA)
The complete silicon-proven DesignWare® IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Securit...
3298
0.0
PCIe 6.0 Controller EP/RP/DM/SW with AMBA bridge & HPC features, including Arm Confidential Compute Architecture
The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 6.0 supports all required features of the PCI Express 6.0 specification...
3299
0.0
PCIe 6.0 Controller IP
The Wolley PCI Express® (PCIe®) Controller IP is a highly configurable, performance-optimized core designed for ASIC and FPGA integration. Supporting ...
3300
0.0
PCIe 6.0 PHY for TSMC N3P
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...