851 10.0

Die-to-Die Controller IP The Synopsys Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accele...

852 10.0

Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm) The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...

853 10.0

Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5) The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...

854 10.0

Differential Clock Receiver - TSMC CLN2P Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...

855 10.0

Differential Clock Receiver - TSMC CLN3A Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...

856 10.0

Differential Clock Receiver - TSMC CLN3E Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...

857 10.0

Differential Clock Receiver to CML - TSMC CLN2P Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...

858 10.0

Differential Clock Receiver to CML - TSMC CLN3A Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...

859 10.0

Differential Clock Receiver to CML - TSMC CLN3E Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...

860 10.0

Differential Clock Receiver to CML - TSMC CLN6FF Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...

861 10.0

Differential Clock Reciever - TSMC CLN3P Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...

862 10.0

Differential Clock Reciever to CML - TSMC CLN3P Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...

863 10.0

Differential Output Buffer - TSMC CLN3P Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a...

864 10.0

Differential Output Buffer - TSMC 6FF Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...

865 10.0

Differential Output Buffer - TSMC CLN3E Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...

866 10.0

Differential Output Buffer - TSMC CLN3P Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...

867 10.0

Differential Output Buffer - TSMC CLN4P Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...

868 10.0

Differential Output Buffer - TSMC N5 Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...

869 10.0

Differential Output Driver - TSMC CLN2P Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...

870 10.0

Differential Receiver - TSMC 7FF Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...

871 10.0

Differential Signal Receiver - TSMC 6FF Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...

872 10.0

Differential Signal Receiver - TSMC N5 Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...

873 10.0

High Performance 1-22.5G PCIe4/SAS4 PHY - TSMC 16FFC Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...

874 10.0

High Performance 20GHz C2C PLL - TSMC CLN3A Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...

875 10.0

High Performance 20GHz C2C PLL - TSMC CLN3E Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...

876 10.0

High Performance 20GHz C2C PLL - TSMC CLN6FF Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...

877 10.0

High Performance 20GHz PLL - TSMC CLN4P Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...

878 10.0

High Performance 20GHz PLL - TSMC CLN5A Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...

879 10.0

High Precision Temp Sensor - TSMC CLN2P Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...

880 10.0

High Precision Temp Sensor - TSMC CLN3A Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...

881 10.0

High Precision Temp Sensor - TSMC CLN3E Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...

882 10.0

High Precision Temp Sensor - TSMC CLN5A Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...

883 10.0

High Speed 20GHz PLL - TSMC CLN6FF Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...

884 10.0

High Speed PLL - TSMC N4P Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...

885 10.0

High Speed PLL - TSMC N5 Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...

886 10.0

High Speed PLL - TSMC N5A Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...

887 10.0

High Speed PLL - TSMC N5A Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...

888 10.0

High Speed PLL CML to Complementary - TSMC CLN3P Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...

889 10.0

Highly scalable inference NPU IP for next-gen AI applications OPENEDGES, the total memory subsystem IP provider, introduces ENLIGHT Pro, a state-of-the-art inference neural processing unit (NPU) IP that outperfor...

890 10.0

TileLink Target TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. Ti...

891 10.0

LIN Bus Master/Slave Controller Core Implements a communication controller that transmits and receives complete Local Interconnect Network (LIN) frames to perform serial communication acc...

892 10.0

MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm) for Automotive Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

893 10.0

MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, N7) for Automotive Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

894 10.0

MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

895 10.0

MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A, N3A) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

896 10.0

MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N5A, N3A) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

897 10.0

MIPI D-PHY TSMC 130nm Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

898 10.0

MIPI D-PHY TSMC 28nm HPC+ @ 2.5Ghz The Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Inte...

899 10.0

MIPI D-PHY Tx-Only 2 Lanes in TSMC (16nm, N7) for Automotive Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

900 10.0

MIPI D-PHY Tx-Only 4 Lanes in TSMC (16nm, N7) for Automotive Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...