1601 1.0

MIPI LLI Controller - (Low Latency Interface) The Low Latency interface (LLI) is a point-to point-interconnect that allows two devices on the separate chips to communicate as if a device attached ...

1602 1.0

MIPI RFFE Master Controller IP Core Mobile radio communication is trending towards complex multi-radio systems comprising of several transceivers. The MIPI RFFE bus is is 2-wire serial i...

1603 1.0

MIPI RFFE Slave Controller IP Core Mobile radio communication is trending towards complex multi-radio systems comprising of several transceivers. The MIPI RFFE bus is is 2-wire serial i...

1604 1.0

MIPI RFFE Slave Controller IP Core v3.0 Mobile radio communication is trending towards complex multi-radio systems comprising several transceivers. Arasan supports the latest MIPI RFFE stand...

1605 1.0

MIPI SLIMbus Device Controller V2.0 The Arasan SLIMbus Device Controller IP is designed to provide MIPI SLIMbus 1.01 compliant connectivity for a peripheral device, like an audio codec, ...

1606 1.0

MIPI SLIMbus Host Controller v2.0 The MIPI SLIMbus Host typically resides in a mobile platform’s application processor and provides two-wire, multi-drop connectivity with multiple audi...

1607 1.0

MIPI SoundWire Master Controller 1.1 The Total MIPI Soundwire IP Solution enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package t...

1608 1.0

MIPI SoundWire Slave Controller 1.1 The Total MIPI Soundwire IP Solution enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package t...

1609 1.0

MIPI UniPro Controller - v1.6 To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and promote open...

1610 1.0

MIPI UniPro Stack - v1.6 To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and promote open...

1611 1.0

BitBLT Graphics Hardware Accelerator (AHB Bus) The Digital Blocks DB9100AHB BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to ...

1612 1.0

BitBLT Graphics Hardware Accelerator (AXI Bus) The Digital Blocks DB9100AXI3 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...

1613 1.0

UMC L130HS 130nm Clock Generator PLL - 160MHz-800MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1614 1.0

UMC L130HS 130nm Clock Generator PLL - 320MHz-1600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1615 1.0

UMC L130HS 130nm Clock Generator PLL - 80MHz-400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1616 1.0

UMC L130HS 130nm DDR DLL - 104MHz-520MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1617 1.0

UMC L130HS 130nm DDR DLL - 78MHz-390MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1618 1.0

UMC L130HS 130nm Deskew PLL - 160MHz-800MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1619 1.0

UMC L130HS 130nm Deskew PLL - 320MHz-1600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1620 1.0

UMC L130HS 130nm Deskew PLL - 80MHz-400MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1621 1.0

UMC L130HS 130nm Spread Spectrum PLL - 160MHz-800MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1622 1.0

UMC L130HS 130nm Spread Spectrum PLL - 320MHz-1600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1623 1.0

UMC L130HS 130nm Spread Spectrum PLL - 80MHz-400MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1624 1.0

UMC L130LL 130nm Clock Generator PLL - 120MHz-600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1625 1.0

UMC L130LL 130nm Clock Generator PLL - 30MHz-150MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1626 1.0

UMC L130LL 130nm Clock Generator PLL - 60MHz-300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1627 1.0

UMC L130LL 130nm DDR DLL - 24MHz-120MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1628 1.0

UMC L130LL 130nm DDR DLL - 32MHz-160MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1629 1.0

UMC L130LL 130nm Deskew PLL - 120MHz-600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1630 1.0

UMC L130LL 130nm Deskew PLL - 30MHz-150MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1631 1.0

UMC L130LL 130nm Deskew PLL - 60MHz-300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1632 1.0

UMC L130LL 130nm Spread Spectrum PLL - 120MHz-600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1633 1.0

UMC L130LL 130nm Spread Spectrum PLL - 30MHz-150MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1634 1.0

UMC L130LL 130nm Spread Spectrum PLL - 60MHz-300MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1635 1.0

UMC L130SP 130nm Clock Generator PLL - 118MHz-590MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1636 1.0

UMC L130SP 130nm Clock Generator PLL - 236MHz-1180MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1637 1.0

UMC L130SP 130nm Clock Generator PLL - 59MHz-295MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1638 1.0

UMC L130SP 130nm DDR DLL - 57MHz-285MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1639 1.0

UMC L130SP 130nm DDR DLL - 76MHz-380MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1640 1.0

UMC L130SP 130nm Deskew PLL - 118MHz-590MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1641 1.0

UMC L130SP 130nm Deskew PLL - 236MHz-1180MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1642 1.0

UMC L130SP 130nm Deskew PLL - 59MHz-295MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1643 1.0

UMC L130SP 130nm Spread Spectrum PLL - 118MHz-590MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1644 1.0

UMC L130SP 130nm Spread Spectrum PLL - 236MHz-1180MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1645 1.0

UMC L130SP 130nm Spread Spectrum PLL - 59MHz-295MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1646 1.0

UMC L150HS 150nm Clock Generator PLL - 140MHz-700MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1647 1.0

UMC L150HS 150nm Clock Generator PLL - 280MHz-1400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1648 1.0

UMC L150HS 150nm Clock Generator PLL - 70MHz-350MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1649 1.0

UMC L150HS 150nm DDR DLL - 57MHz-285MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1650 1.0

UMC L150HS 150nm DDR DLL - 76MHz-380MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...