1951 1.0

TSMC CLN28LP 28nm General Purpose PLL - 160MHz-800MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

1952 1.0

TSMC CLN28LP 28nm Multi Phase DLL - 160MHz-800MHz The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

1953 1.0

TSMC CLN28LP 28nm Multi Phase DLL - 320MHz-1600MHz The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

1954 1.0

TSMC CLN28LP 28nm Multi Phase DLL - 80MHz-400MHz The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

1955 1.0

TSMC CLN28LP 28nm Spread Spectrum PLL - 140MHz-700MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1956 1.0

TSMC CLN28LP 28nm Spread Spectrum PLL - 280MHz-1400MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1957 1.0

TSMC CLN28LP 28nm Spread Spectrum PLL - 70MHz-350MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1958 1.0

TSMC CLN40G 40nm Clock Generator PLL - 170MHz-850MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1959 1.0

TSMC CLN40G 40nm Clock Generator PLL - 340MHz-1700MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1960 1.0

TSMC CLN40G 40nm Clock Generator PLL - 680MHz-3400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1961 1.0

TSMC CLN40G 40nm DDR DLL - 150MHz-750MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1962 1.0

TSMC CLN40G 40nm DDR DLL - 200MHz-1000MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1963 1.0

TSMC CLN40G 40nm DDR DLL - 316MHz-1580MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1964 1.0

TSMC CLN40G 40nm Deskew PLL - 170MHz-850MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1965 1.0

TSMC CLN40G 40nm Deskew PLL - 340MHz-1700MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1966 1.0

TSMC CLN40G 40nm Deskew PLL - 680MHz-3400MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1967 1.0

TSMC CLN40G 40nm General Purpose PLL - 340MHz-1700MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

1968 1.0

TSMC CLN40G 40nm Multi Phase DLL - 170MHz-850MHz The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

1969 1.0

TSMC CLN40G 40nm Multi Phase DLL - 340MHz-1700MHz The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

1970 1.0

TSMC CLN40G 40nm Multi Phase DLL - 680MHz-3400MHz The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

1971 1.0

TSMC CLN40G 40nm Spread Spectrum PLL - 150MHz-750MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1972 1.0

TSMC CLN40G 40nm Spread Spectrum PLL - 300MHz-1500MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1973 1.0

TSMC CLN40G 40nm Spread Spectrum PLL - 600MHz-3000MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1974 1.0

TSMC CLN40LP 40nm Clock Generator PLL - 150MHz-750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1975 1.0

TSMC CLN40LP 40nm Clock Generator PLL - 300MHz-1500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1976 1.0

TSMC CLN40LP 40nm Clock Generator PLL - 75MHz-375MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1977 1.0

TSMC CLN40LP 40nm DDR DLL - 112MHz-560MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1978 1.0

TSMC CLN40LP 40nm DDR DLL - 177MHz-885MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1979 1.0

TSMC CLN40LP 40nm DDR DLL - 84MHz-420MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1980 1.0

TSMC CLN40LP 40nm Deskew PLL - 150MHz-750MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1981 1.0

TSMC CLN40LP 40nm Deskew PLL - 300MHz-1500MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1982 1.0

TSMC CLN40LP 40nm Deskew PLL - 75MHz-375MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1983 1.0

TSMC CLN40LP 40nm General Purpose PLL - 150MHz-750MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

1984 1.0

TSMC CLN40LP 40nm Multi Phase DLL - 150MHz-750MHz The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

1985 1.0

TSMC CLN40LP 40nm Multi Phase DLL - 300MHz-1500MHz The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

1986 1.0

TSMC CLN40LP 40nm Multi Phase DLL - 75MHz-375MHz The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

1987 1.0

TSMC CLN40LP 40nm Spread Spectrum PLL - 150MHz-750MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1988 1.0

TSMC CLN40LP 40nm Spread Spectrum PLL - 300MHz-1500MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1989 1.0

TSMC CLN40LP 40nm Spread Spectrum PLL - 75MHz-375MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1990 1.0

TSMC CLN55GP 55nm Clock Generator PLL - 130MHz-650MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1991 1.0

TSMC CLN55GP 55nm Clock Generator PLL - 260MHz-1300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1992 1.0

TSMC CLN55GP 55nm Clock Generator PLL - 520MHz-2600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1993 1.0

TSMC CLN55GP 55nm DDR DLL - 150MHz-750MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1994 1.0

TSMC CLN55GP 55nm DDR DLL - 200MHz-1000MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1995 1.0

TSMC CLN55GP 55nm DDR DLL - 316MHz-1580MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1996 1.0

TSMC CLN55GP 55nm Deskew PLL - 130MHz-650MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1997 1.0

TSMC CLN55GP 55nm Deskew PLL - 260MHz-1300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1998 1.0

TSMC CLN55GP 55nm Deskew PLL - 520MHz-2600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1999 1.0

TSMC CLN55GP 55nm General Purpose PLL - 260MHz-1300MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

2000 1.0

TSMC CLN55GP 55nm Multi Phase DLL - 130MHz-650MHz The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....