3051 0.0

Simulation VIP for NVMe The Cadence® Verification IP (VIP) for NVMe is part of Cadence's storage interface VIP portfolio. It provides a mature and highly capable compliance v...

3052 0.0

Simulation VIP for OCP In production since 2011 for dozens of designs....

3053 0.0

Simulation VIP for OctaRam In production since 2018 for many production designs....

3054 0.0

Simulation VIP for ONFi In production since 2011 for dozens of production designs....

3055 0.0

Simulation VIP for OSPI NOR In production since 2012 for dozens of designs....

3056 0.0

Simulation VIP for PCIe Used by all leading PCIe, IP, and SoC design verification teams for all generations....

3057 0.0

Simulation VIP for PIPE PHY The Cadence® PIPE PHY Verification IP (VIP) provides a mature, highly capable verification solution for the PHY layer of complex protocols such as PCI...

3058 0.0

Simulation VIP for PLB In production since 2011....

3059 0.0

Simulation VIP for PMBus Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for PMBus provides a complete bus functional model (BFM), integrated aut...

3060 0.0

Simulation VIP for Q-SPI In production since 2018 for many production designs....

3061 0.0

Simulation VIP for SAS The Cadence® Verification IP (VIP) for SAS is part of Cadence’s broad storage interface verification IP (VIP) portfolio. Serial Attached SCSI (SAS) ha...

3062 0.0

Simulation VIP for SD CARD and SDIO In production since 2012 for many production designs....

3063 0.0

Simulation VIP for SMBus Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for SMBus provides a complete bus functional model (BFM), integrated aut...

3064 0.0

Simulation VIP for SPDIF Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the SPDIF protocol provides a complete bus ...

3065 0.0

Simulation VIP for SPI This Cadence® Verification IP (VIP) provides support for the SPI protocol. The SPI VIP provides a complete bus functional model (BFM) and integrated a...

3066 0.0

Simulation VIP for SPI NAND In production since 2016 for many production designs....

3067 0.0

Simulation VIP for TileLink This Cadence® Verification IP (VIP) provides support for the TileLink specification. It provides a highly capable compliance verification solution sim...

3068 0.0

Simulation VIP for Toggle NAND In production since 2011 for many production designs....

3069 0.0

Simulation VIP for UART Best-in-class UART Verification IP for your IP, SoC and system-level design testing. In production since 2014 on dozens of production designs....

3070 0.0

Simulation VIP for UCIE Best-in-class UCIe Verification IP for your IP, SoC, and system-level design testing....

3071 0.0

Simulation VIP for UCIE Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Universal Chiplet Interconn...

3072 0.0

Simulation VIP for UFS In production since 2012 on multiple production designs....

3073 0.0

Simulation VIP for USB The Cadence® Verification IP (VIP) for USB is a complete VIP solution for the Universal Serial Bus Revision 3.2 Specification and errata. It provides ...

3074 0.0

Simulation VIP for USB4 Used by all top market leaders semiconductor companies....

3075 0.0

Simulation VIP for xSPI xSPI in production since 2019 for many production designs....

3076 0.0

Single Channel HDLC Controller Inicore's iniHDLC family of High-Level Data Link Controller (HDLC) cores consist of a Receiver (FPR: From Primary Rate) and a Transmitter (TPR: To Pri...

3077 0.0

PipelineZero 32-bit Embedded Processor The BA20 is a small, ultra-low-power, and very efficient 32-bit processor. It is an excellent step up from the 8051 and other 8- and 16-bit microcontr...

3078 0.0

MIPI C-PHY 2.1 TX/RX, 6nm InPsytech proudly presents our groundbreaking innovation, the MIPI C-PHY Ver2.1 IP, setting new standards in connectivity solutions. Designed to empow...

3079 0.0

MIPI C-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP The MXL-CPHY-2p5G-CSI-2-TX+-T-40ULP is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Maste...

3080 0.0

MIPI C-PHY DSI RX (Transmitter/Host) IP in TSMC 22ULL The MXL-CPHY-2p5G-DSI-RX-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...

3081 0.0

MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in GlobalFoundries (12nm) for Automotive Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3082 0.0

MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in Samsung (SF2P) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3083 0.0

MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes for TSMC 12FFCP Synopsys’ integrated DesignWare C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and...

3084 0.0

MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in GlobalFoundries (12nm) for Automotive Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3085 0.0

MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in Samsung (SF2P) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3086 0.0

MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in Samsung (SF5A, SF4A) for Automotive Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3087 0.0

MIPI C-PHY v2.0 D-PHY v2.1 for TSMC N5A Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3088 0.0

MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in Samsung (SF2A, SF4A) for Automotive Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3089 0.0

MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N7, N5A, N3A) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3090 0.0

MIPI C-PHY v2.0 D-PHY v2.1 RX for GF 12LP+ Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3091 0.0

MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6 Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3092 0.0

MIPI C-PHY v2.0 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (N7) for Automotive Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3093 0.0

MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in Samsung (SF5A, SF4A) for Automotive Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3094 0.0

MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (N7) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3095 0.0

MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (N7, N6, N6C) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

3096 0.0

MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) in TSMC 40ULP The MXL-CDPHY-CSI-2-TX-T-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification...

3097 0.0

MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP The MXL-CDPHY-CSI-2-TX-T-65LP is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Master supp...

3098 0.0

MIPI C-PHY/D-PHY Combo CSI-2 TX 3.5Gsps/trio in TSMC 28nm The MXL-CDPHY-3p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...

3099 0.0

MIPI C-PHY/D-PHY Combo CSI-2 TX 4.5Gsps/trio in TSMC 28nm The MXL-CDPHY-4p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...

3100 0.0

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps, 2T/2L The MXL-CDPHY-CSI-2-TX+-40LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification f...