401 20.0

MIPI D-PHY Rx-Only 4 Lanes in GF (28nm, 12nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

402 20.0

MIPI D-PHY Rx-Only 4 Lanes in SMIC (40nm, 28nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

403 20.0

MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

404 20.0

MIPI D-PHY Rx-Only 4 Lanes in UMC (28nm, 22nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

405 20.0

MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

406 20.0

MIPI D-PHY Tx-Only 4 Lanes in GF (12nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

407 20.0

MIPI D-PHY Tx-Only 4 Lanes in SMIC (28nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

408 20.0

MIPI D-PHY Tx-Only 4 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6, N6C) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

409 20.0

MIPI D-PHY Tx-Only 4 Lanes in UMC (28nm, 22nm) Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...

410 20.0

MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...

411 20.0

MIPI DSI-2 host/device controllers for high-speed serial interface between application processor and displays Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...

412 20.0

MIPI I3C controller delivers high bandwidth and scalability for integration of multiple sensors Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...

413 20.0

MIPI M-PHY G4 Type 1 1Tx1RX in TSMC (16nm, 12nm, N5) The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...

414 20.0

MIPI M-PHY G4 Type 1 2TX2RX in GF (12nm) The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...

415 20.0

MIPI M-PHY G5 Type 1 2Tx2Rx in Samsung (14nm) The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...

416 20.0

MIPI UniPro IP for reliable, high-performance and low power link between devices in mobile devices Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...

417 20.0

eMMC 5.1 Host Controller The eMMC 5.1 Host Controller IP from Arasan Chip Systems is a highly integrated host controller IP solution. This IP handles all of the timing and ...

418 20.0

eMMC LDPC Encoder/Decoder Mobiveil’s eMMC LDPC Encoder/Decoder is an advanced flash reliability solution engineered to maximize flash endurance and retention. Featuring industr...

419 20.0

IO 1.2V GPIO in Samsung (4nm) Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

420 20.0

IO 1.8V GPIO in Samsung (4nm) Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

421 20.0

IO 1.8V LVDS Automotive Grade 1 GF (22nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

422 20.0

IO 1.8V LVDS in GF (22nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

423 20.0

IO 1.8V LVDS Rx in GF (12nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

424 20.0

IO 3.3V eMMC in GF (22nm) Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

425 20.0

IO 3.3V LVDS Rx Automotive Grade 2 in GF (12nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

426 20.0

IO 3.3V LVDS Rx in GF (12nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

427 20.0

IO GPIO in TSMC for Automotive Grade 1 (22nm) Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

428 20.0

IO I2C 3.3V in GF (22nm) Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters ...

429 20.0

IO I3C 3.3V in GF (22nm) Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

430 20.0

IP Prototyping Kits for USB, DDR, MIPI, PCI Express protocols The Synopsys IP Prototyping Kits, part of the IP Accelerated initiative, center around a complete, out-of-the-box reference design that consists of a ...

431 20.0

LPDDR4 multiPHY V2 in GF (22nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

432 20.0

LPDDR4 multiPHY V2 in Samsung (14nm, 11nm, 10nm, 8nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

433 20.0

LPDDR4 multiPHY V2 in TSMC (28nm, 22nm, 16nm, 12nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

434 20.0

LPDDR4/3, DDR4/3 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

435 20.0

LPDDR4X multiPHY in GF (14nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

436 20.0

LPDDR4X multiPHY in Samsung (14nm, 11nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

437 20.0

LPDDR4X multiPHY in TSMC (16nm, 12nm,N7, N6) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

438 20.0

LPDDR4X multiPHY Plus in GF (12nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

439 20.0

LPDDR4x/4 PHY IP for 22nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

440 20.0

LPDDR5/4/4X PHY in GF (12nm) The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...

441 20.0

LPDDR5/4/4X PHY in TSMC (16nm, 12nm, N7, N6, N5) The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...

442 20.0

LPDDR5/4x/4 combo PHY on 14nm, 12nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

443 20.0

LPDDR5X/5/4X PHY in Samsung (8nm, SF4X, SF2) The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...

444 20.0

LPDDR5X/5/4X/4 combo PHY at 12nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

445 20.0

LPDDR5X/5/4X/4 combo PHY at 7nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

446 20.0

LPDDR5X/5/4X/4 PHY for 16nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

447 20.0

LPDDR5X/5/4X/4 PHY IP for 12nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

448 20.0

GPIO 1.8V Automotive Grade 1 in GF (22nm) Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

449 20.0

GPIO 1.8V FS Automotive Grade 1 in GF (22nm) Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

450 20.0

Arasan xSPI + eMMC Combo PHY IP This IP integrates both xSPI (Expanded Serial Peripheral Interface) and eMMC 5.1 PHY (Physical Layer) into a single unified solution, enabling support...