Design & Reuse
1613 IP
951
100.0
Post-Quantum Cryptography - xQlave® PQC ML-DSA (Dilithium)
The xQlave® ML-DSA (Dilithium) Digital Signature Algorithm IP core secures critical infrastructures and operations against the threat of quantum compu...
952
100.0
LPDDR5X, LPDDR5, LPDDR4X, LPDDR4 Combo PHY & Controller
The INNOSILICON™ LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller. It is fully compliant with the JEDEC standard. Optimized for low-power a...
953
80.0
GDDR7 PHY & Controller
The INNOSILICON™ GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode. In PAM3 mode, each b...
954
60.0
UCIe Chiplet PHY & Controller
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
955
51.0
TLS 1.3 - Security Protocol
Transport Layer Security (TLS) is a cryptographic protocol used for building a secure connection between a client and a server over the Internet. A ha...
956
51.0
True Random Number Generator (TRNG)
The TRNG IP core establishes a benchmark for hardware-based security in cryptographic systems, by generating high-entropy, true random numbers essenti...
957
50.0
MAXVY Technologies
MAXVY is a fast growing fabless semiconductor company which is currently engaged in the fields of RTL design and Verification IP Solutions. We offe...
958
50.0
AES - GCM - Extreme-speed variant
XIP1113E is a an extreme-speed IP core implementing the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). AES-GCM is a widely used cryp...
959
50.0
IPsec - Security Protocol
IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s IPsec core enhances secure...
960
48.0
nQrux® Crypto Module
Xiphera’s nQrux® Crypto Module IP core provides a comprehensive security platform that allows for customisation of top-notch cryptographic services, s...
961
43.0
Elliptic Curve Cryptography (ECC) Accelerator
The high-speed ECC Accelerator reaches to more than a thousand operations per second in a modern FPGA or ASIC. Furthermore, it covers all NIST P curve...
962
25.0
HBM4, HBM3E PHY & Controller
INNOSILICON™ HBM4/3E IP is fully compliant with the JEDEC standard for HBM3E and the preliminary specification for HBM4. The IP includes a customizabl...
963
25.0
DDR5, DDR4 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR5/4 Combo PHY s provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDR...
964
15.0
GDDR6X, GDDR6 Combo PHY & Controller
The INNOSILICON™ GDDR6X/6 PHY is fully compliant with the JEDEC GDDR6X/6 standard, supporting data rates of up to 20 Gbps per pin for PAM2 GDDR6 mode ...
965
10.0
MIPI DSI-2 Transmitter Interface IP
MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile dev...
966
8.0
MIPI I3C Verification IP with IBI feature enabled
The Maxvy's MIPI-I3C VIP provides configurable option to select I3C master/secondary master/slave based on the MIPI I3C DUT function as per user speci...
967
8.0
Universal Chiplet Interconnect Express (UCIe) Verification IP
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of you...
968
5.0
MIPI I3C Master RISC-V based subsystem
RISC-V based MAXVY MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a ...
969
5.0
MIPI SPMI Target Controller
The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...
970
5.0
MIPI-I3C Combo Host and Target interface controller IP for Sensor and Peripheral connection
The MIPI I3C (Improved Inter Integrated circuit) is a two wire bidirectional Serial Bus for sensor communication. The MIPI I3C interface has been ...
971
5.0
MIPI-I3C Combo IP Host/Target HDR-DDR compliance with Spec v1.1.1
MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication. The MIPI I3C interface has been develope...
972
3.0
Pseudorandom Number Generator (PRNG) - Balanced variant
The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...
973
3.0
Pseudorandom Number Generator (PRNG) - High-speed variant
The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...
974
2.0
HBM3, HBM3E PHY & Controller
This document describes a general layout scheme and Innosilicon HBM3/3E PHY connecting to the controller using a DFI digital interface. All interface ...
975
2.0
MIPI A-PHY Verification IP
MIPI A-PHY v1.0 is a physical layer communication protocol designed for automotive applications, including driver assistance, autonomous driving, and ...
976
2.0
Innosilicon - High-Quality ASIC Customization Services
With a team of first-class experts, highly-reliable chip customization ability, and rich experience in mass production on processes from 55nm to 5nm, ...
977
1.0
10G Multi-SerDes PHY
The Innosilicon 10G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 10Gbps within a single lane. The PHY can be configured ...
978
1.0
12.5G Multi-SerDes PHY
The Innosilicon 12.5G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 12.5Gbps within a single lane. For this particular da...
979
1.0
32G Multi-SerDes For PCIe5.0/USB3.x PHY
The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this datasheet, the PH...
980
1.0
32G Multi-SerDes PHY + Controller
The INNOSILICON™ 32G Multi-SerDes PHY is a highly configurable IP solution capable of supporting data rates of up to 32 Gbps per lane. It is designed ...
981
1.0
64G/56G SerDes
The Innosilicon 64G/56G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 56Gbps within a single lane. For this datasheet, th...
982
1.0
25G Multi-SerDes PHY
The Innosilicon 25G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datash...
983
1.0
HBM2E PHY&Controller
Innosilicon HBM2E PHY IP is a silicon proven product with max speed up to 3600Mbps per DQ data, HBM2E memory has 1024bit DQ, total bandwidth can be 3....
984
1.0
HBM2E/2 Combo PHY&Controller
Innosilicon HBM2E/2 Combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible HBM devices. It is optimized ...
985
1.0
HBM3/2E Combo PHY&Controller
The third-generation HBM (HBM3/2E) technology, outlined by the JESD235C standard, inherits physical 128-bit DDR interface with 2n/4n prefetch architec...
986
1.0
PCIe 4.0 Controller
The Innosilicon Gen1/2/3/4 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, hig...
987
1.0
PCIe 4.0 PHY
The Innosilicon PCIe4.0 PHY is a highly configurable PHY capable of supporting speeds up to 16Gbps within a single lane. For this particular datasheet...
988
1.0
PCIe 6.0, CXL3.0 PHY & Controller
INNOSILICON™ PCIe 6.0 and CXL 3.0 IP solutions combines a high-performance controller and PHY and is fully compliant with PCIe 6.0, CXL 3.0, and PIPE ...
989
1.0
MCR DDR5 PHY
The INNOSILICON DDR Mixed-Signal MCR DDR5 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible MCR DDR5 DIMM...
990
1.0
HDMI1.4 Receiver PHY
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from an HDMI source device for display applications. Innosilicon H...
991
1.0
HDMI1.4 Transmitter IP
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
992
1.0
HDMI2.0 Receiver PHY
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from an HDMI source device for display applications. Innosilicon H...
993
1.0
HDMI2.0 Receiver PHY & Controller
Innosilicon HDMI RX IP is composed of the digital controller, the PHY logic and physical layer. The digital controller receives video, audio, synchron...
994
1.0
HDMI2.0 TX Controller
Innosilicon HDMI TX Controller is designed for transmitting video and audio data from a video source device to a display device, which is compatible w...
995
1.0
HDMI2.0 TX PHY
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
996
1.0
HDMI2.0/1.4 RX PHY & Controller
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from a HDMI source device for display applications, which is compat...
997
1.0
HDMI2.0/1.4 TX PHY & Controller
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
998
1.0
HDMI2.1 Transmitter PHY & Controller
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
999
1.0
HDMI2.1 TX Controller
Innosilicon HDMI TX Controller is designed for transmitting video and audio data from a video source device to a display device, which is compatible w...
1000
1.0
HDMI2.1 TX PHY
Innosilicon HDMI TX PHY IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with ...