1 5.0

DiFi IP core The DiFi IP core is a highly scalable and silicon agnostic implementation of the IEEE-ISTO Std 4900-2021: Digital IF Interoperability Standard v1.2.1 ...

2 200.0

CC-6xx CryptoManager Core The Rambus CryptoManager Core CC-6xx is a standalone symmetric cipher-only subsystem of the CryptoManager Hub CH-6xx. The CC-6xx products are designed...

3 200.0

CC-7xx CryptoManager Core The automotive-grade Rambus CryptoManager Core CC-7xx family is a standalone symmetric cipher-only subsystem of the CryptoManager Hub CH-7xx. The CC-7...

4 190.0

MIPI CSI-2 Controller Core V2 The Rambus CSI-2 Controller Core V2 is the second generation CSI-2 controller core. It is further optimized for high performance, low power and small ...

5 190.0

MIPI DSI-2 Controller Core The Rambus DSI-2 Controller Core is the second generation DSI controller core. It is further optimized for high performance, low power and small size....

6 125.0

SOS Core - Design Data and IP Management Design data management platform for small to mid-sized teams, supporting analog, mixed-signal, digital, RF, and microwave designs with reliable versio...

7 120.0

12 bit 5Msps SAR ADC IP core Engineered for performance and efficiency, this 12-bit SAR ADC IP Core delivers up to 5 mega samples per second while consuming minimal power, making ...

8 110.0

Ethernet Enterprise Switch/Router IP Core - Efficient and Massively Customizable Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...

9 100.0

Securyzr™ neo Core Platform - One core, multiple products Securyzr™ neo Core Platform is Secure-IC’s enhanced version of its flagship offering Securyzr™ integrated Secure Element (iSE) Series. Thanks to its c...

10 100.0

Aeonic Generate Digital PLL for multi-instance, core logic clocking The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality digital PLL that enables distributed clocking for per-c...

11 100.0

eFPGA IP as a synthesizable RTL core For ASIC and SoCs designers who need fast, right-the-first time design and fast time to volume, Menta is unique in our ability to deliver proven eFPGA...

12 70.0

Ultra-Fast Baseline and Extended JPEG Encoder Core This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implement...

13 50.0

CAN 2.0B Bus Controller IP Core The Controller Area Network (CAN) controller IP that implements the CAN2.0A, CAN2.0B as well as newer high performance Non ISO CAN-FD protocols. It ca...

14 50.0

High Bandwidth Out-of-Order RISC-V CPU IP Core ...

15 50.0

High Bandwidth Out-of-Order RISC-V CPU IP Core ...

16 50.0

Ultra-Fast Baseline and Extended JPEG Decoder Core This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements ...

17 46.0

Ultra Low Power AI core Akida Pico accelerates a set of highly optimized temporal event-based neural network models to create an ultra energy-efficient, and purely digital, e...

18 45.0

AES - GCM Authenticated Encryption / Decryption Security Core The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bi...

19 40.0

Baseline and Extended JPEG Decoder Core The JPEG-DX-S Decoder decompresses JPEG images and the video payload for Mo-tion-JPEG container formats. It accepts compressed streams of images with ...

20 40.0

Baseline and Extended JPEG Decoder Core The JPEG-DX-S IP core is an area-efficient, high-performance JPEG decoder conforming to the Baseline Sequential DCT and the Extended Sequential DCT mo...

21 40.0

Baseline and Extended JPEG Encoder Core This JPEG compression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an...

22 40.0

Baseline JPEG Encoder Core This JPEG compression IP core supports the Baseline Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-perfor...

23 40.0

MIPI RFFE Master Controller IP Core v3.0 Mobile radio communication systems are complex multi-radio systems comprising several transceivers. Arasan supports the latest MIPI RFFE standard v3.0...

24 40.0

Ultra-Fast AVC / H.264 Compression Baseline Profile Encoder Core The H264-E-BPF IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It Implements an u...

25 30.0

TicoXS | JPEG XS Decoder IP core JPEG XS has been co-developed by intoPIX and standardized by ISO (ISO/IEC 21122). TicoXS decoder is a visually lossless, ultra-lightweight and ultra-l...

26 30.0

TicoXS | JPEG XS Encoder IP core JPEG XS has been co-developed by intoPIX and standardized by ISO (ISO/IEC 21122). TicoXS encoder is a visually lossless, ultra-lightweight and ultra-l...

27 30.0

zstd compression and decompression IP core The zstd (Zstandard) compression algorithm is an advanced, lossless data compression technology. It has quickly become a popular choice for a variety ...

28 30.0

Quad core IP platform with integrated Arm security subsystem Aion Silicon (formerly Sondrel) has created a powerful, quad core IP platform, the SFA 200, that is ideal for ASIC solutions for remote gathering and ...

29 30.0

NVM Express Host IP Core The IPM-NVMe_Host core is a verilog IP to be integrated in a FPGA or ASIC design. It fully manages the NVMe and PCIe protocol on the host side without...

30 30.0

LZ4 compression and decompression IP core The LZ4 compression algorithm is a fast, lossless data compression technology renowned for its high-speed performance and low latency. LZ4 offers impr...

31 26.0

HDMI 2.0b IP Core The Bitec HDMI 2.0b IP Core enables HDMI interconnectivity without the need for external HDMI ASSP devices. Supporting pixel clocks to 600Mhz, the IP ...

32 26.0

HDMI 2.1 IP Core The Bitec HDMI 2.1b IP Core enables HDMI interconnectivity in FPGA or ASIC devices. Supporting uncompressed video formats to 8K60 4:2:0 and beyond for...

33 26.0

VESA Display Stream Compression (DSC) IP Core Display Stream Compression offers inter-operable, visually lossless real-time, video compression to satisfy the emerging high bandwidth and high resol...

34 26.0

DisplayPort 1.4a IP Core DisplayPort heralds a new alternative in video connectivity. Designed to enable low cost direct drive monitors and backed by industry leaders (Intel, ...

35 25.0

Low-Latency AVC / H.264 Decompression Baseline Profile Decoder Core The H264-D-BP IP core is a video decoder complying with the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It implements a...

36 25.0

Low-Power AVC / H.264 Compression Baseline Profile Encoder Core The H264-E-BPS IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard It Implements an en...

37 25.0

DVB-S2 Demodulator IP Core DVBS2_DEMOD.vhd performs the demodulation based on three tracking loops: carrier tracking (for coherent demodulation), symbol timing tracking, and A...

38 20.0

Secure-IC's Securyzr™ Memory & Bus Protection IP Core The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory. It supports AHB/AXI sl...

39 20.0

AES Encryption / Decryption Security Core The AES encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit bl...

40 20.0

TicoXS FIP Decoder IP core with JPEG XS and intoPIX Flawless Imaging Profile (FIP) – The newest codec for AV over IP with 100% quality and zero latency ! TicoXS FIP is the smart path to AV over IP. With low logic & low memory, it delivers together the interoperable JPEG XS lightweight low latency compre...

41 20.0

TicoXS FIP Encoder IP core with JPEG XS and intoPIX Flawless Imaging Profile (FIP) – The newest codec for AV over IP with 100% quality and zero latency ! TicoXS FIP is the smart path to AV over IP. With low logic & low memory, it delivers together the interoperable JPEG XS lightweight low latency compre...

42 20.0

Image warping IP core The image warping IP core TW100 builds on TAKUMI's graphics accelerator IP core family as an additional solution to a variety of distortion correcting...

43 20.0

Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk) KJN-S1 is able to get Higher performance lossless Compression by original algorithm. This product achieves a smaller circuit scale and higher compress...

44 20.0

Multi Protocol Switch IP Core for Safe and Secure Ethernet Network "The CetraC Switch IP core is the ideal solution to interconnect any Ethernet, TSN and ARINC 664 Part 7 (AFDX) equipment for safety critical applicati...

45 20.0

Multi Protocol Switch IP Core for Safe and Secure Ethernet Network "The CetraC Switch IP core is the ideal solution to interconnect any TSN, Ethernet and ARINC 664 Part 7 (AFDX) equipment for safety critical applicati...

46 20.0

DVB-S2 LDPC BCH Decoder and Encoder IP Core The DVB-S2 LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite....

47 20.0

DVB-S2X LDPC BCH Decoder and Encoder IP Core The DVB-S2X LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 design fo...

48 16.0

RISC-V Processor - RV12 - 32/64 bit, Single Core CPU The RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of ...

49 15.0

68000 - D68000-CPU32 - 16/32-bit Microprocessor The D68000-CPU32 soft core is binary-compatible with the industry standard 68000’s CPU32 version of the 32-bit microcontroller. The D68000-CPU32 has a...

50 15.0

IEEE1588 & IEEE802.1AS PTP Ordinary Clock (OC) core The PTP Ordinary Clock (OC) from NetTimeLogic is an extension to a single port of NetTimeLogic's PTP Transparent Clock (TC). It adds the Sync and Anno...