101 8.0

CRYSTALS Dilithium core for accelerating NIST FIPS 204 Module Lattice Digital Signature algorithm eSi-Dilithium is a hardware core for accelerating the high-level operations specified in the NIST FIPS 204 standard. Dilithium is an integral part o...

102 8.0

CRYSTALS Kyber core for accelerating NIST FIPS 203 Key Encapsulation Mechanism eSi-Kyber is a hardware accelerator core designed to accelerate post-quantum Key Encapsulation Mechanism (KEM) as defined by NIST FIPS 203. Kyber, a...

103 8.0

FSPI - DFSPI - SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption) The DFSPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial cl...

104 8.0

OSPI - DOSPI - Serial Peripheral Interface - Master/Slave with single, dual, quad and octal SPI Bus support The DOSPI is a revolutionary octal SPI designed to offer the fastest operations available for any serial SPI memory. It is flexible enough to interfac...

105 7.0

Falcon IP Core Falcon IP Core is a post-quantum digital signature algorithm (DSA). It is currently under development. It is going to be compliant with Falcon specifi...

106 7.0

ECDSA IP Core ECDSA IP Cores perform digital signature generation and verification in compliance with the Elliptic Curve Digital Signature Algorithm (ECDSA) specifi...

107 7.0

AES GCM IP Core AES GCM IP Core is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in "FIPS 197"...

108 7.0

AES IP Core AES IP Core is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in "FIPS 197". Th...

109 7.0

SHA3 IP Core SHA3 IP Cores perform cryptographic hashing in compliance with the SHA-3 (Secure Hash Algorithm 3) specifications defined in 'FIPS 202'. This standard...

110 7.0

Dilithium IP Core Dilithium IP Core is a post-quantum digital signature algorithm (DSA). It currently supports Sign and Verify functions, with key generation functional...

111 7.0

DRBG IP Core DRBG IP Cores perform deterministic random bit generation in compliance with the standards and guidelines defined in 'NIST SP 800-90A'. This standard ...

112 7.0

TRNG IP Core TRNG IP Cores perform true random number generation in compliance with the standards and guidelines defined in 'NIST SP 800-90B'. This standard specif...

113 7.0

RSA IP Core RSA IP Cores perform digital signature generation and verification in compliance with the RSA (Rivest-Shamir-Adleman) Digital Signature Algorithm spec...

114 7.0

RSA Keygen IP Core RSA Keygen IP Cores perform key generation in compliance with the RSA Key Pair Generation specifications defined in 'FIPS 186'. This standard specifie...

115 7.0

USB 2.0 Full/Low-Speed Device Core The FHG USB DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-speed USB 2.0 device functionality wi...

116 7.0

USB 2.0 High/Full-Speed Device Core The FHG USB2 DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high-/full-speed USB 2.0 device functiona...

117 7.0

USB 2.0 OTG Full/Low-Speed Dual Role Core The FHG USB OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 device and host ...

118 7.0

USB 2.0 OTG High/Full/Low-Speed Dual Role Core The FHG USB2 OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high/full/low-speed USB 2.0 device and ...

119 7.0

KYBER IP Core Kyber IP is a core designed for Kyber post-quantum Key Encapsulation Mechanism (KEM). It currently supports the Encapsulation and Decapsulation functi...

120 6.0

I2C Master/Slave Controller Core IP I2C Master/Slave Controller core implements a bidirectional serial interface compatible with the NXP’s I2C bus specification and supports all transfer...

121 6.0

UART : Universal Asynchronous Receiver Transmitter Core Universal Asynchronous Receiver Transmitter Core performs serial-to-parallel conversion on data characters received from a peripheral device or a MODE...

122 6.0

SMART - DSMART - ISO 7816 Based Smart Card Reader The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications. It provides a communication interface with a sm...

123 5.0

80251 - DQ80251 - Revolutionary Quad-Pipelined Ultra High Performance Microcontroller The DQ80251 is a revolutionary Quad-Pipelined ultra high performance, speed optimized soft core of a 16-bit/32-bit embedded microcontroller. The core ...

124 5.0

I3C - DI3CM-HCI - MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus. Keeping the best assets from its elder brother, the I3C has major improve...

125 5.0

64-bit CPU Core with Level-2 Cache Controller The 64-bit AX27L2 is a 5-stage processor that supports the latest RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit comp...

126 5.0

256-bit SHA Crypto Processor Core The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for m...

127 5.0

CAN 2.0, CAN FD - Developed as ISO26262-10 Safety Element out of Context (ISO26262 soft IP SEooC, ASIL-B ready design) Introducing DCD’s Ingenious CAN FD IP Core: Empowering Engineers with Unparalleled Flexibility. When it comes to seamlessly infusing cutting-edge C...

128 5.0

SATA Device IP Core (1.5, 3.0, 6.0 Gbps) The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage ...

129 5.0

WAVE677DV PX4, AV1, H.265, HEVC, H.264, AVC, VP9 dual core video codec IP for 8K with YUV422, 444 support WAVE677DV PX4 is a 4K/8K multi-standard video codec HW IP that supports AV1, HEVC/H.265, AVC/H.264, and VP9 standards. It provides 4K120fps@500MHz, 8K...

130 5.0

DCRP1A - 100% Secure Cryptographic System for RSA, Diffie-Hellman and ECC with AMBA AHB, AXI4 and APB The CryptOne, a 100% secure cryptographic system, has been based on more than 20 years DCD’s market experience. Starting from 1999, Digital Core Desig...

131 5.0

CCSDS AR4JA LDPC Decoder & Encoder IP Core AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3 and 3/4). To obtain hi...

132 5.0

HDLC - DHDLC - HDLC/SDLC controller The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390. It allows to save MCU...

133 5.0

IEEE802.11n/ac/ax Wi-Fi LDPC Decoder and Encoder IP Core - silicon proven The 802.11n/ac/ax LDPC decoder is developed for high throughput WLAN applications....

134 5.0

SerDes Hard Macro-IP in GlobalFoundries 22FDX Low-power, flexible and robust Serializer-de-serializer IP built upon a proven ring-PLL based architecture, Support for multiple protocols, as well a...

135 5.0

AES - DAES XTS - Cryptographic co-processor for lightweight cryptography DAES XTS IP Core from Digital Core Design is a compact cryptographic co-processor designed to seamlessly implement the Rijndael encryption algorithm i...

136 5.0

SHA - DSHA2-256 - SHA IP Core with native SHA2-256 HMAC support The DSHA2-256 is a universal solution which efficiently accelerates SHA2-256 hash function compliant with FIPS PUB 180-4. It computes message digest i...

137 5.0

AHB Cache Controller Core The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave AHB processor interface and a 32-bit master AHB interface to the...

138 5.0

The FortifyIQ Compact AES-SX AES Encryption Core with Robust SCA/FI Protection for Constrained Devices FortifyIQ’s Compact AES IP Core is an ultra-lightweight hardware accelerator optimized for resource-constrained embedded systems that require secure e...

139 5.0

High Throughput Elliptic Curve Cryptography hardware acceleration Core eSi-ECDSA-HT is a High Throughput (HT) Elliptic Curve Cryptography (ECC) hardware acceleration core, which supports EC Digital Signature Algorithm (EC...

140 5.0

Time Sensitive Networking (TSN) IIC(R) Plugfest Application core The TSN Industrial Internet Consortium(R) (IIC) Plugfest Application is a companion core for the TSN IP cores from NetTimeLogic. The IIC(R) Plugfest A...

141 5.0

MIPI RFFE Master IP Core The MIPI RFFE Master controller IP is a highly optimized and technology agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ASIC an...

142 5.0

MIPI RFFE Slave IP Core The MIPI RFFE Slave controller IP is a highly optimized and technology and PHY agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ...

143 5.0

Visually LossLess compression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS) TMC’s JPEG XS encoder / decoder IP is Visually LossLess compression / decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). T...

144 5.0

Visually LossLess decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS) TMC’s JPEG XS encoder / decoder IP is Visually LossLess decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). The logic gate ...

145 5.0

Ultra Compact 32-bit RISC-V CPU Core AndesCore™ N22 is a 32-bit 2-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications that require low energy consumpti...

146 5.0

DMESCC - Enhanced Multiprotocol Serial Communication Controller The DEMSCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit microprocessors. The DMESCC...

147 5.0

Compact High-Speed 32-bit CPU Core AndesCore™ N25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of delivering high per-...

148 5.0

Compact High-Speed 32-bit CPU Core AndesCore™ N25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of delivering high per-...

149 5.0

Compact High-Speed 32-bit CPU Core with DSP AndesCore™ D25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of delivering high per-...

150 5.0

Compact High-Speed 32-bit CPU Core with Level-2 Cache The 32-bit A27L2 is a 5-stage processor that supports the latest RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compr...