Design & Reuse
8402 IP
1951
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MIPI Transmitter 80Mbps~1.5Gbps ; UMC 28nm HPC Logic Process
MIPI Transmitter 80Mbps~1.5Gbps ; UMC 28nm HPC Logic Process...
1952
0.118
MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process
MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process...
1953
0.118
MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process
MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process...
1954
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MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC process
MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC process...
1955
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MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC+ process
MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC+ process...
1956
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MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process
MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process...
1957
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MIPI Transmitter CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process
MIPI Transmitter CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process...
1958
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Direct memory access controller with AHB interface
Direct memory access controller with AHB interface....
1959
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Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC Process.
Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC Process....
1960
0.118
HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)
HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)...
1961
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HJTC 0.11um pflash process standard synchronous high density single port SRAM memory compiler.
HJTC 0.11um pflash process standard synchronous high density single port SRAM memory compiler....
1962
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HJTC 0.11um uLL/pFlash Single Port SRAM compiler
HJTC 0.11um uLL/pFlash Single Port SRAM compiler...
1963
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HJTC 0.11um uLL/pFlash via1 ROM memory compiler.
HJTC 0.11um uLL/pFlash via1 ROM memory compiler....
1964
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HJTC 0.18um pFlash Process synchronous High Density, Low Power mini single port SRAM
HJTC 0.18um pFlash Process synchronous High Density, Low Power mini single port SRAM...
1965
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Flash Memory Controller IP, Support NAND type Flash memory of 8MB - 2 GB, 24 ECC bits per 512 bytes, Soft IP
NAND-type Flash Controller with AHB interface which supports page size for 512B and 2KB, data width for 8/16-Bit and DMA handshaking protocol....
1966
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Flash Memory Controller IP, Support page sizes of 512, 2K, 4K, 8K and 16K bytes NAND Flash memory, 74bit ECC correction (512 or 1K bytes sectors), Soft IP
Nand Flash Controller with AHB Interface over 74-Bit ECC correction capacity....
1967
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Flash Memory pre-fetcher controller with AHB lite system
Flash Memory pre-fetcher controller with AHB lite system...
1968
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DLL (All Digital) IP, Input: 200MHz - 533MHz, Output: 200MHz - 533MHz, UMC 65nm LP process
Input 200M-533MHz, output 200M-533MHz, all digital DLL with two-channel DQS delay range, UMC 65nm LP/RVT Low-K Logic process....
1969
0.118
DLL (All Digital) IP, Input: 300MHz - 600MHz, Input: 300MHz - 600MHz, UMC 40nm LP process
An ADDLL operate at 300MHz~600MHz.Output 0-180 degree Phase adjustment range.Delay adjustment resolution <= 1% of reference clockUMC 40nm LP/RVT Logic...
1970
0.118
DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz (Programmable output delay stepping with 1/64 clock period), UMC 55nm SP process
Input 333M-800MHz, output 333M-800MHz, all digital DLL with per 1/64UI programmable delay, UMC 55nm SP/RVT Low-K Logic process....
1971
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DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 40nm LP process
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range, UMC 40nm LP/RVT Low-K Logic process....
1972
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DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 55nm LP process
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range, UMC 55nm LP/RVT Low-K Logic process....
1973
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DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 55nm SP process
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range, UMC 55nm SP/RVT Low-K Logic process....
1974
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DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 65nm LP process
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range, UMC 65nm LP/RVT Low-K Logic process....
1975
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DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 65nm SP process
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range, UMC 65nm SP/RVT Low-K Logic process....
1976
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DLL (All Digital) IP, Input: 333MHz - 800MHz, Output: 333MHz - 800MHz, UMC 90nm SP process
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range, UMC 90nm SP/RVT Low-K Logic process....
1977
0.118
DLL (All Digital) IP, Input: 360MHz - 720MHz, Output: 360MHz - 720MHz, UMC 40nm LP process
Input 360M-720MHz, output 360M-720MHz, DLL, Output 0-180 degree Phase adjustment range. UMC 40nm LP process....
1978
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DLL (All Digital) IP, Input: 5MHz - 70MHz, Output: 5MHz - 70MHz, UMC 40nm LP process
An ADDLL operate at 5MHz~70MHz.Output produce a rising/falling edge delay tuning clock.UMC 40nm LP/RVT Logic process....
1979
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PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Advanced Enhancement) 2T Logic process....
1980
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PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Advanced Enhancement) 2T Logic process....
1981
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PLL (All Digital, Spread Spectrum) IP, Input: clock range:10MHz - 1280MHz, Output: 15.625MHz - 2GHz, Spreading depth: -10%(max), Spreading Freq: 20KHz to 300KHz, UMC 0.11um HS/AE process
Input clock range:10M ~ 1280MHz, output clock range:15.625M ~ 2000MHz wide-range SSCG, UMC 0.11um HS/AE (AL Advanced Enhancement) 2T Logic process....
1982
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PLL (De-Skew) IP, Input: 15MHz - 110MHz, Output: 15MHz - 110MHz, UMC 0.13um HS/FSG process
Input 15M-110MHz, output 15M-110MHz, De-skew PLL with 0.9V~1.32V power supply range, UMC 0.13um HS/FSG Logic process....
1983
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PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, HJTC 0.18um eFlash/G2 process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, HJTC 0.18 eFlash process....
1984
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PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process....
1985
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PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process....
1986
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 55nm LP process
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process....
1987
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.11um HS/AE process
Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL, UMC 0.11um HS/AE Logic process, It has lock detector function....
1988
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PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.13um SP/FSG process
Input 10M-200MHz, output 25M-400MHz, frequency synthesizable PLL, UMC 0.13um SP/FSG Logic process....
1989
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PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 300MHz - 600MHz, UMC 55nm SP process
Input 10M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 55nm SP Low-K Logic process....
1990
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 300MHz - 600MHz, UMC 90nm SP process
Input 10M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process....
1991
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PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process....
1992
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PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process....
1993
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PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process....
1994
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PLL (Frequency Synthesizer) IP, Input: 10MHz - 500MHz, Output: 31.25MHz - 500MHz, UMC 65nm SP process
Input 10M-500MHz, Output 31.25M-500MHz, frequency synthesizer PLL, UMC 65nm SP/RVT Low-K process....
1995
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PLL (Frequency Synthesizer) IP, Input: 10MHz - 50MHz, Output: 10MHz - 200MHz, UMC 40nm LP process
Input 10-50MHz, output 10-200MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process....
1996
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PLL (Frequency Synthesizer) IP, Input: 10MHz - 50MHz, Output: 10MHz - 200MHz, UMC 40nm LP process
Input 10-50MHz, output 10-200MHz, frequency synthesizable PLL, UMC 40nm LP/RVT Logic process(Note:same schematic with FXPLL010HH0L, but Poly Density E...
1997
0.118
PLL (Frequency Synthesizer) IP, Input: 10MHz, Output: 40MHz - 60MHz, HJTC 0.18um eFlash/G2 process
Input 10MHz, output 40M-60MHz, frequency synthesizable PLL, HJTC 0.18um eFlash process....
1998
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PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um MS process
Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um Logic/MIXEDMODE AE process....
1999
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PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um MS process
Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um Logic/MIXEDMODE AE process....
2000
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PLL (Frequency Synthesizer) IP, Input: 10MHz-200MHz, Output: 25MHz - 400MHz, UMC 0.11um SP/FSG process
Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL, UMC 0.11um SP/FSG Logic process....