eMemory Technology Inc. IP Cores

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2501

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell...

2502

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell...

2503

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell....

2504

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell....

2505

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell...

2506

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

2507

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell....

2508

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell....

2509

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell...

2510

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell...

2511

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell....

2512

0.118

UMC 55nm ULP/LowK process Single-Port SRAM

UMC 55nm ULP/LowK process Single-Port SRAM...

2513

0.118

UMC 55nm ULP/LowK process Single-Port SRAM

UMC 55nm ULP/LowK process Single-Port SRAM...

2514

0.118

UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler

UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler...

2515

0.118

UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler

UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler...

2516

0.118

UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler

UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler...

2517

0.118

UMC 55nm ULP/LowK Process via ROM compiler for well bias

UMC 55nm ULP/LowK Process via ROM compiler for well bias...

2518

0.118

UMC 55nm ULP/LowK Process via1 ROM compiler well bias

UMC 55nm ULP/LowK Process via1 ROM compiler well bias...

2519

0.118

UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT

UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT...

2520

0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell...

2521

0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)...

2522

0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell.

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell....

2523

0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...

2524

0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)...

2525

0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...

2526

0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell.

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell....

2527

0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell...

2528

0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell.

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell....

2529

0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...

2530

0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)...

2531

0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...

2532

0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

2533

0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

2534

0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

2535

0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

2536

0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias...

2537

0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

2538

0.118

UMC 55nm uLP/uHVT LowK Logic Process Ultra High Density (6T) Generic Core Cell Library

UMC 55nm uLP/uHVT LowK Logic Process Ultra High Density (6T) Generic Core Cell Library...

2539

0.118

UMC 55uLP_x005F_x005F_x005F_x000D_ ADC

UMC 55uLP ADC...

2540

0.118

UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony

UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony...

2541

0.118

UMC 65nm LL/RVT 1P10M LowK Logic Process 1.8V/3.3V multi-voltage generic I/O cell library

UMC 65nm LL/RVT 1P10M LowK Logic Process 1.8V/3.3V multi-voltage generic I/O cell library...

2542

0.118

UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler.

UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler....

2543

0.118

UMC 65nm SP/RVT Logic Process MPCA cell library

UMC 65nm SP/RVT Logic Process MPCA cell library...

2544

0.118

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy.

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy....

2545

0.118

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....

2546

0.118

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....

2547

0.118

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.

UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....

2548

0.118

UMC 80nm HV Process High Density Standard Cell Library

UMC 80nm HV Process High Density Standard Cell Library...

2549

0.118

UMC 80nm HV Process PG Single-Port SRAM Memory Compiler_x005F_x005F_x005F_x005F_x005F_x000D_

UMC 80nm HV Process PG Single-Port SRAM Memory Compiler...

2550

0.118

UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy

UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy...

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