Design & Reuse
8401 IP
401
1.0
MCR DDR5 PHY
The INNOSILICON DDR Mixed-Signal MCR DDR5 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible MCR DDR5 DIMM...
402
1.0
HDMI1.4 Receiver PHY
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from an HDMI source device for display applications. Innosilicon H...
403
1.0
HDMI1.4 Transmitter IP
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
404
1.0
HDMI2.0 Receiver PHY
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from an HDMI source device for display applications. Innosilicon H...
405
1.0
HDMI2.0 Receiver PHY & Controller
Innosilicon HDMI RX IP is composed of the digital controller, the PHY logic and physical layer. The digital controller receives video, audio, synchron...
406
1.0
HDMI2.0 TX Controller
Innosilicon HDMI TX Controller is designed for transmitting video and audio data from a video source device to a display device, which is compatible w...
407
1.0
HDMI2.0 TX PHY
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
408
1.0
HDMI2.0/1.4 RX PHY & Controller
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from a HDMI source device for display applications, which is compat...
409
1.0
HDMI2.0/1.4 TX PHY & Controller
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
410
1.0
HDMI2.1 Transmitter PHY & Controller
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
411
1.0
HDMI2.1 TX Controller
Innosilicon HDMI TX Controller is designed for transmitting video and audio data from a video source device to a display device, which is compatible w...
412
1.0
HDMI2.1 TX PHY
Innosilicon HDMI TX PHY IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with ...
413
1.0
5G Multi-SerDes For PCIe2.0/USB3.0 PHY
The Innosilicon 5Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 5Gbps within a single lane. For this datasheet, the P...
414
1.0
8G Multi-SerDes For PCIe3.0/USB3.0 PHY
The Innosilicon 8Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 8Gbps within a single lane. For this datasheet, the P...
415
1.0
Wireline Transceiver
This IP can be used for BPSK RF communication through a signal wire. Originally it was designed for use with V1 USB PD. However, it is a generic block...
416
1.0
PLL for TSMC 130nm LP
The OT3122t130 is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for the TSMC 0.13µ LP or ...
417
1.0
Core Voltage Regulator
The OT1104 is a CMOS 75mA on-chip core voltage regulator designed for use when a pin for an external decoupling capacitor is not available. A source...
418
1.0
Low Dropout Linear Regulator
The OT1105t180 is a 150mA CMOS low dropout regulator designed for use in a wide variety of mixed signal device applications. It is designed for use wi...
419
1.0
Low Power Clock Multiplier PLL for 40nm TSMC ULP CMOS
The OT3135 is a flexible low power clock multiplier PLL function with a wide range of input and output frequencies, and is designed for TSMC 40nm, ULP...
420
1.0
Power On Reset
The OT0403 is a CMOS general purpose POR for 3.3V. It provides a minimum 8uS reset pulse with power rise times of 0 to infinity. It also provide a bro...
421
1.0
DP/eDP1.4/1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
422
1.0
DP/eDP1.4/1.2 TX PHY&controller
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...
423
1.0
LPDDR4X/4 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR4 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devi...
424
1.0
LPDDR4X/4/3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR4X/4/3 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM...
425
1.0
LPDDR5, LPDDR4X, LPDDR4 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR5/4/4X COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible...
426
1.0
USB 2.0 DRD Controller
Innosilicon USB2.0 DRD Controller provides a USB2.0-compliant host/device controller solution. This controller can be programmed to support data trans...
427
1.0
USB 3.0 DRD Controller
Innosilicon USB3.0 DRD Controller provides a USB3.0-compliant host/device controller solution. This controller can be programmed to support data trans...
428
1.0
USB2.0 OTG PHY
The INNO USB 2.0 PHY conforms to the specification of UTMI+ level 3 Revision 1.0 (USB 2.0 Transceiver Macrocell Interface Plus) and has excellent perf...
429
1.0
USB2.0/eUSB2.0 PHY & Controller
USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications. Innosilicon provides a comprehensive se...
430
1.0
USB3.1/3.0 PHY & Controller
The Innosilicon USB3.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface fo...
431
1.0
USB3.2 PHY & Controller
INNOSILICON™ USB3.2 Controller and PHY IP is a highly customizable IP module that converts high-speed serial data into parallel data, and is compliant...
432
1.0
StarFive -RISC-V design services and training
Founded in 2018, StarFive is a Chinese local high-tech company with independent intellectual properties. As the leader of the RISC-V software and hard...
433
50.0
40G UCIe PHY for high-density advanced packages
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...
434
50.0
40G UCIe PHY for organic substrate standard packages
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...
435
50.0
11-bit, 5 GSPS Analog to Digital Converter (ADC) IP block - GlobalFoundries 22nm
The A11B5G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a hybrid-SAR ADC, with 11-bit r...
436
50.0
12-bit, 9 GSPS High Performance Swift™ DAC in 16nm CMOS
The ODT-DAC-12B9G-16 is a high performance current steering 12-bit 9GSPS DAC on 16nm CMOS process that operates at an update rate of up to 9GSPS. The ...
437
50.0
32G PHY in TSMC (16nm, 12nm, N7, N6, N5, N5A, N4C, N3E, N3P)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
438
50.0
I3C Host Controller
The MIPI I3C interface is an evolutionary standard that improves upon the features of I2C, while maintaining backward compatibility. This standard off...
439
50.0
56G Ethernet PHY in TSMC (16nm, 12nm)
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
440
50.0
CAN 2.0B Bus Controller IP Core
The Controller Area Network (CAN) controller IP that implements the CAN2.0A, CAN2.0B as well as newer high performance Non ISO CAN-FD protocols. It ca...
441
50.0
WAVE-J, 8-bit, 12-bit JPEG Codec IP upto 64Kx64K New!
Chips&Media WAVE-J is a standalone and high-performance JPEG codec IP that can perform JPEG Baseline/Extended and MJPEG decoding and encoding. Com...
442
50.0
WAVE517, AV1, H.265, HEVC, H.264, AVC, VP9, AVS2 video decoder IP for 4K
The world-leading hardware IP provider, Chips&Media, pre-released the multi-standard HW IP named WAVE517, targeting 4K ultra-high-definition (UHD), wh...
443
50.0
WAVE521C, H.265, HEVC, H.264, AVC video codec IP for 4K
WAVE521C is a 4K multi-format codec IP to support both HEVC/H.265 and AVC/H.264 video standards. This IP core provides real-time performance for encod...
444
50.0
WAVE627, AV1, H.265, HEVC, H.264, AVC, video encoder IP for 4K
WAVE627 is a 4K multi-standard video encoder HW IP that supports AV1, HEVC/H.265, and AVC/H.264 video codec standards. It provides 4K60fps@500MHz real...
445
50.0
WAVE633, H.265, HEVC, H.264, AVC, video codec IP for 4K
WAVE633 is a 4K multi-standard video codec HW IP that supports HEVC/H.265 and AVC/H.264 video codec standard. It provides 4K60fps@500MHz real-time enc...
446
50.0
HBM3 PHY V2 in TSMC (N5, N4P, N3E)
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
447
50.0
PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
448
50.0
PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N4P, N4C, N3E, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
449
50.0
PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Expre...
450
50.0
PCIe Gen5 NVMe SSD RAMDISK Reference Platform
Mobiveil’s RAMDISK-Gen5is a PCIe Gen5 and 1.4 NVMe compliant Ramdisk that emulates the next generation NVMe Gen5 SSDs with high performance. With hi...