Design & Reuse
3729 IP
1251
0.118
DDR DLL IP, 100MHz - 200MHz, Output: 13.5% - 36.6% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhanceme...
1252
0.118
DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.13um HS/FSG process....
1253
0.118
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic ...
1254
0.118
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/RVT Logic process....
1255
0.118
DDR DLL IP, Input: 100MHz - 150MHz, Output: 100MHz - 150MHz, UMC 0.18um G2 process
Input 100M-150MHz, output 100M-150MHz, DDR DLL, UMC 0.18um GII Logic process....
1256
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.13um HS/FSG process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....
1257
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.15um SP process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.15um SP Logic process....
1258
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.162um LL process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.162um Logic process....
1259
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.18um GII Logic process....
1260
0.118
DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process
Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process....
1261
0.118
DDR DLL IP, Input: 192MHz - 400MHz, Output: 96MHz - 200MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG process DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage....
1262
0.118
DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process
Input 200-333MHz, output 200-333MHz, DDR2 DLL, UMC 90nm SP/RVT Low-K Logic process....
1263
0.118
DDR DLL IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, UMC 55nm SP process
Input 200-400MHz, output 200-400MHz, DDR2 DLL, UMC 55nm SP Low-K Logic process....
1264
0.118
DDR DLL IP, Input: 333MHz - 667MHz, Output: 333MHz - 667MHz, UMC 90nm SP process
Input 333M-667MHz, output 333M-667MHz, DDR2/3 Multi-phase DLL, UMC 90nm SP/RVT Low-K Logic process....
1265
0.118
DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller usage....
1266
0.118
DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process
Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....
1267
0.118
DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process
Input 66M-200MHz, output 66M-200MHz, DDR DLL, UMC 90nm SP/RVT Low-K Logic process....
1268
0.118
DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process
Input 80-320MHz, output 6.25%~50% delay, 80-320MHz, DDR2 DLL, UMC 55nm SP/RVT Low-K Logic process....
1269
0.118
DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...
1270
0.118
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...
1271
0.118
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process...
1272
0.118
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process...
1273
0.118
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process...
1274
0.118
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process...
1275
0.118
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process...
1276
0.118
DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process
DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process...
1277
0.118
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process...
1278
0.118
DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process
DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process...
1279
0.118
DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process
DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process...
1280
0.118
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process...
1281
0.118
DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process
DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process...
1282
0.118
DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process
DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process...
1283
0.118
DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process
DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process...
1284
0.118
DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess
DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess...
1285
0.118
DDR2/3 Controller IP, DDR2/3 controller with DFI 2.1 interfaces, Support DDR1/DDR2/DDR3 SDRAM, Soft IP
DDR2/3 Combo SDRAM Controller....
1286
0.118
DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process
DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process...
1287
0.118
DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process
DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process...
1288
0.118
DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process
DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process...
1289
0.118
DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process
DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process...
1290
0.118
DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process
DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process...
1291
0.118
DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device
DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device...
1292
0.118
DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device
DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device...
1293
0.118
DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...
1294
0.118
DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process
DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process...
1295
0.118
DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process
DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process...
1296
0.118
DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process
DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process...
1297
0.118
DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process
DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process...
1298
0.118
DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process
DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process...
1299
0.118
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device...
1300
0.118
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage...