Design & Reuse
3730 IP
2301
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell...
2302
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell.
UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell....
2303
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...
2304
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)...
2305
0.118
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...
2306
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2307
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2308
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2309
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2310
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias...
2311
0.118
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2312
0.118
UMC 55nm uLP/uHVT LowK Logic Process Ultra High Density (6T) Generic Core Cell Library
UMC 55nm uLP/uHVT LowK Logic Process Ultra High Density (6T) Generic Core Cell Library...
2313
0.118
UMC 55uLP_x005F_x005F_x005F_x000D_ ADC
UMC 55uLP ADC...
2314
0.118
UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony
UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony...
2315
0.118
UMC 65nm LL/RVT 1P10M LowK Logic Process 1.8V/3.3V multi-voltage generic I/O cell library
UMC 65nm LL/RVT 1P10M LowK Logic Process 1.8V/3.3V multi-voltage generic I/O cell library...
2316
0.118
UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler.
UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler....
2317
0.118
UMC 65nm SP/RVT Logic Process MPCA cell library
UMC 65nm SP/RVT Logic Process MPCA cell library...
2318
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy....
2319
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
2320
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
2321
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
2322
0.118
UMC 80nm HV Process High Density Standard Cell Library
UMC 80nm HV Process High Density Standard Cell Library...
2323
0.118
UMC 80nm HV Process PG Single-Port SRAM Memory Compiler_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 80nm HV Process PG Single-Port SRAM Memory Compiler...
2324
0.118
UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy
UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy...
2325
0.118
UMC 80nm LL/eHV Process synchronous Via ROM memory compiler
UMC 80nm LL/eHV Process synchronous Via ROM memory compiler...
2326
0.118
UMC 90nm LL-RVT (Low-K) Process with 3.3V device analog esd IO group (with BOAC)
UMC 90nm LL-RVT (Low-K) Process with 3.3V device analog esd IO group (with BOAC)...
2327
0.118
UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC BOAC Pad
UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC BOAC Pad...
2328
0.118
UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC pad
UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC pad...
2329
0.118
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO...
2330
0.118
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm LL/RVT LowK process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO...
2331
0.118
UMC 90nm LL/RVT MPCA core cell library
UMC 90nm LL/RVT MPCA core cell library...
2332
0.118
UMC 90nm LL/RVT process MULTI-VOLTAGE GENERIC I/O CELL USING 3.3V GOX52 IO
UMC 90nm LL/RVT process MULTI-VOLTAGE GENERIC I/O CELL USING 3.3V GOX52 IO...
2333
0.118
UMC 90nm Logic/Mixed Mode SP(RVT) Low-K process;True 3.3V PECL IO Library.
UMC 90nm Logic/Mixed Mode SP(RVT) Low-K process;True 3.3V PECL IO Library....
2334
0.118
UMC 90nm SP RVT process SSTL18 IO cell library
UMC 90nm SP RVT process SSTL18 IO cell library...
2335
0.118
UMC 90nm SP-HVT LowK Logic Process High Speed PowerSlash Kit
UMC 90nm SP-HVT LowK Logic Process High Speed PowerSlash Kit...
2336
0.118
UMC 90nm SP-RVT LowK Logic Process High Speed PowerSlash Kit
UMC 90nm SP-RVT LowK Logic Process High Speed PowerSlash Kit...
2337
0.118
UMC 90nm SP/RVT Low-K process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm SP/RVT Low-K process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO...
2338
0.118
UMC 90nm SP/RVT LowK Logic Process ECO M1 core cell library
UMC 90nm SP/RVT LowK Logic Process ECO M1 core cell library...
2339
0.118
UMC 90nm SP/RVT process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO
UMC 90nm SP/RVT process true 3.3V Analog ESD IO cell Library Using 3.3V GOX52 IO...
2340
0.118
UMC 90nm SPLVT ultra-high speed 1-port SRAM
UMC 90nm SPLVT ultra-high speed 1-port SRAM...
2341
0.118
UMC 90nm Standard Performance LowK Logic Process Synchronous high density single port register file SRAM memory compiler
UMC 90nm Standard Performance LowK Logic Process Synchronous high density single port register file SRAM memory compiler...
2342
0.118
CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process
CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process...
2343
0.118
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process...
2344
0.118
An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process.
An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process....
2345
0.118
Analog Comparator; 0.25um Logic process
Analog Comparator; 0.25um Logic process...
2346
0.118
Analog Front End IP for CMOS image processing applications
FXAFE010HF0A is an Analog Front End IP for CMOS image processing applications. FXAFE010HF0A is fabricated in UMC 55nm SP, low-k, logic process to enab...
2347
0.118
Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process.
Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process....
2348
0.118
Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process
Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process...
2349
0.118
One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), Support retention and deep sleep modes with built-in power gating circuitry., UMC 55nm LP process
UMC 55um LP Low-K process One Port Register File compiler....
2350
0.118
One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), UMC 55nm LP process
UMC 55nm LP Logic process 0.425um2-Bit cell One Port Register File memory compiler....