Design & Reuse

PLL (Frequency Synthesizer) IP, Input: 200MHz - 400MHz, Output: 800MHz - 1600M, 400MHz - 800MHz and 200MHz - 400MHz, UMC 55nm SP process

Input 200M-400MHz, output 800M-1600M, 400-800MHz and 200-400MHz, frequency synthesizable PLL, UMC 55nm SP/RVT Low-K Logic process....