Design & Reuse
Catalog of SIP Cores
System on Chip design resources

DLL IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 25% delay in period of FREF, UMC 28nm Logic and Mi...