Design & Reuse
Catalog of SIP Cores
System on Chip design resources

PLL (Frequency Synthesizer) IP, Input: 10MHz, Output: 40MHz - 60MHz, HJTC 0.18um eFlash/G2 process

Input 10MHz, output 40M-60MHz, frequency synthesizable PLL, HJTC 0.18um eFlash process....