Design & Reuse
Catalog of SIP Cores
System on Chip design resources

PLL (Frequency Synthesizer) IP, Input: 1MHz - 200MHz, Output: 25MHz - 380MHz, UMC 0.18um G2 process

Input 1M-200MHz, output 25M-380MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process....