Design & Reuse
Catalog of SIP Cores
System on Chip design resources

PLL (Frequency Synthesizer) IP, Input: 4MHz - 200MHz, Output: 20MHz - 400MHz, UMC 0.18um G2 process

Input 4M-200MHz, output 20M-400MHz, frequency synthesizable PLL, UMC 0.18um GII Logic process....