Design & Reuse
Catalog of SIP Cores
System on Chip design resources

MS18: 1.2-1.8V GPIO with 1.8V/5V analog/RF, 20-36V HV analog & OTP cell, TSMC 180nm

A silicon-proven Certus I/O library for TSMC 180nm, built to fill gaps in the native foundry I/O offering at this node. It pairs a 1.2–1.8V GPIO (dual...