Company
design-reuse.com
D&R China
Blogs
Industry Articles
D&R Events
IP-SoC Days 2026
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC 2025
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
Videos
Subscribe to D&R SoC News Alert
English
Mandarin
Login
Catalog of SIP Cores
System on Chip design resources
Catalog of SIP Cores
System on Chip design resources
Menu
Home
Search IP Core
News
Blogs
Articles
D&R Events
Videos
Subscribe to D&R SoC News Alert
Login
News
Center
Foundation IP
Analog IP
Interface IP
Interconnect IP
Memory Controller & PHY
Peripheral Controller
Wireless IP
Wireline IP
Processor IP
RISC-V
AI Core
Automotive IP
Security IP
IoT
Media IP
Avionics / Space IP
Verification IP
Verification Platform
Design Platform
Asic & IP Design Center
IP-SoC Days
IP-SoC Days 2026
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC 2025
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
Standard Cell (ECO) Library IP, RVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 12-Track ECO Core Cell Library....
You must be registered with the D&R website to view the full search results, including:
Complete datasheets for products
Contact Suppliers for information
Login
Email
Password
Forgot your password ?
Keep me signed in.
New to D&R ?
Create your D&R account
