LVDS Receiver IP, Clock: 16 MHz - 120 MHz, 6:42 data lane expansion for throughput up to 5040 Mbps, UMC 40nm LP process
LVDS RX, UMC 40nm LP/RVT Low-K Logic process....
You must be registered with the D&R website to view the full search results, including:
-
Complete datasheets for products
- Contact Suppliers for information
