Design & Reuse
Catalog of SIP Cores
System on Chip design resources

3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process

3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process...