Catalog of SIP Cores
System on Chip design resources

Catalog of SIP Cores
System on Chip design resources
- Home
- Search IP Core
- News
- Blogs
- Articles
- D&R Events
- Videos
- Subscribe to D&R SoC News Alert
- Login

News
Center arrow_down

IP-SoC Days arrow_down

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell...

You must be registered with the D&R website to view the full search results, including:

Complete datasheets for products
Contact Suppliers for information