Design & Reuse
Catalog of SIP Cores
System on Chip design resources

AHB5 SG Multi-Channel DMA Controller (configurable 1 to 126 DMA Channels, configurable 64, 128, 256 or 512 bits data path)

The Digital Blocks DB-DMAC-MCn-AHB5 SystemVerilog RTL IP Core is a Scatter-Gather (SG) Direct Memory Access (DMA) Controller for AMBA 5 AHB systems, w...