Design & Reuse
Catalog of SIP Cores
System on Chip design resources

AXI4 SG Multi-Channel DMA Controller (fixed 2,4,8,16 DMA Channels, fixed 64, 128 or 256 bits data path)

The Digital Blocks DB-DMAC-MCn-AXI4 SystemVerilog RTL IP Core is a Scatter-Gather (SG) Direct Memory Access (DMA) Controller for AMBA AXI4 systems wit...