Design & Reuse
Catalog of SIP Cores
System on Chip design resources

56G Ethernet and PCIe 6.x Combo PHY (8nm) 8LPU

The SERDES PHY includes the functions of both PCIe PHY and Ehternet PHY. The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe...