Design & Reuse
Catalog of SIP Cores
System on Chip design resources

UCIe 2.0 PHY & Controller (Standard & Advanced Package) in 8nm, 5nm, 4nm (8LPU, SF5A, SF4X)

UCIe 2.0 PHY Overview: The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT...