Henderson, Nevada, April 18, 2005 * * * Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of Riviera 2005.04 with an all new system-level simulation engine and improved SystemC (TM) debugging. Riviera is based on Aldec's industry-proven VHDL and Verilog mixed-language simulation technology used by ASIC and high-density FPGA designers for new generation system-on-chip designs.
Riviera 2005.04 includes an all new simulation technology designed for use in system-level verification. The System-Level Platform (SLP) incorporates a completely redesigned simulation engine that dramatically reduces simulation run times for gate-level and timing verification. This new simulation technology integrates seamlessly with the current environment and is completely transparent to the designer. Riviera with SLP will simulate any designs containing Verilog netlists and automatically distribute simulation tasks between the new SLP engine and the standard simulation engine. In addition to the Verilog performance, the new release has decreased VHDL timing simulation runtimes by as much as 3X through further optimization of the VITAL libraries.
SystemC (TM) Debugging
Riviera 2005.04 has extended the support for SystemC, now allowing a history of the SystemC signal to be stored and displayed from the Riviera simulation database (.asdb). Signal breakpoints can be set on SystemC signals for value, event, and transaction. The latest release also includes a pre-installed gcc package and precompiled SystemC Verification libraries (SCV) to simplify the setup.
"The increased Verilog and VHDL simulation performance of Riviera 2005.04 will provide an enormous gain to our already industry standardized simulation performance," stated Eric Seabrook, director of marketing for Aldec. "Adding the improvements for co-simulation with SystemC and MATLAB provides a completely new level of support from Aldec for system-level design."
In addition to the Simulink interface, Riviera now offers the ability to co-simulate directly with MATLAB. The interface bridges the gap between the mathematical computation, analysis, visualization, algorithm development environment and the HDL hardware modeling and simulation environment. It allows for direct calling and visualization of any built-in or M-language functions from Verilog or VHDL.
All three assertion languages including OpenVera assertions (OVA), Property Specification Language (PSL) and SystemVerilog assertions (SVA) have been improved for both VHDL and Verilog. Riviera 2005.04 also includes the ability to generate VCD output for VHDL providing engineers with an industry standard printing format of the simulation results.
Pricing and Availability
Riviera 2005.04 is available today based on a floating OS-independent license that supports UNIX, Windows® and Linux. Pricing for Riviera 2005.04 begins at U.S. $12,450.00 and is sold directly by Aldec in the U.S. as well as by authorized international distributors. For a FREE evaluation copy of Riviera, go to www.aldec.com/riviera.
Riviera, a high-performance verification tool, is based on Aldec's industry-proven VHDL and Verilog mixed-language simulation technology and is used by ASIC and high-density FPGA designers for new generation system-on-chip designs. It supports IEEE VHDL 1076-87/93 and VITAL 2000 in addition to Verilog 1364-2001 and SystemVerilog. Code coverage, Waveform Viewer, advanced dataflow, Design Profiler and interfaces to other EDA tools are provided via PLI and VHPI function calls as part of Riviera's product configuration.
Aldec, Inc., a 21-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers' needs with its offices located around the globe. Continuous innovation, superior product quality and a total commitment to customer service comprise the foundation of Aldec's strategic objectives. Additional information about Aldec is available at http://www.aldec.com.
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Riviera is a trademark of Aldec, Inc. SystemC is a trademark of the Open SystemC Initiative. MATLAB and Simulink are trademarks of The Mathworks. All other trademarks or registered trademarks are property of their respective owners.