A matter of the design chain

Most commercial IP is high-integrity and low-risk. It has usually been proven in silicon on tens, hundreds or possibly thousands of designs across a large number of processes. A similar argument can be made for commercial design tools. The user community for leading EDA tools is huge. By and large, EDA tool quality is outstanding. Occasionally, a design may fail because a simulation or verification step was not performed thoroughly, but rarely is a tool to blame.

The third critical piece of the puzzle is the foundry's own process models, DRC flows, etc. Even the smallest issue with this level of process abstraction can lead to poor results. Most foundries have become expert at establishing and exhaustively testing these models. Still, it is common for a new process to undergo a transition once volume experience is gained from early customer designs.

The circuitry newly created by the designers will rely totally on the accuracy of the process information, the analysis of the design tools and the skill of the design team. This is where the opportunity is and where the strong design chain partnerships that exist among the foundry, EDA vendors, IP vendors, flow developers and, of course, the actual chip design team come into play.

By Mark Templeton, president and chief executive officer of Artisan Components Inc.